EP80579 Datasheet, PDF (153/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-21. Summary of SATA Interface Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The CMD and PIE[0-3] registers support error enabling and masking.
Logging Details The SATA interface captures the type of event detected in the STS and PIS[0-3] registers.
Reporting Multiple
Errors
The SATA interface does not capture multiple events.
Data Poisoning IICH backbone does not support data poisoning.
For additional details on error handling in the SATA interface, see Section 23.0, “SATA:
Bus 0, Device 31, Function 2”.
5.4.6
Serial I/O Interface
The IICH provides a serial I/O interface that can generate an interrupt on error events.
Table 5-22 summarizes the error conditions that the serial I/O interface captures.
.
Table 5-22. Summary of Serial I/O Interface Error Conditions
Event
Type
Fatality^a
Reports via
Notes
Framing Error
Parity Error
Overrun Error
Uncorrectable
Uncorrectable
Uncorrectable
Fatal
Fatal
Fatal
Interrupt
Interrupt
Interrupt
Received character missing stop bit.
Received character has parity error.
Receive buffer over-written.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-23 summarizes the capabilities of the thermal sensor error handling for each of
the features that the unit is expected to provide.
Table 5-23. Summary of Serial I/O Interface Error Reporting Capabilities
Feature
Enabling and Masking Error
Reporting
Logging Details
Reporting Multiple Errors
Data Poisoning
Implementation
The IER and LCR registers supports error enabling and masking.
The serial I/O interface captures the type of event detected in the IIR and
LSR registers.
The serial I/O interface does not capture multiple events.
N/A
For additional details on error handling in the serial I/O interface, see Section 33.0,
“Serial I/O Unit and Watchdog Timer”.
5.5
Error Reporting by the System Memory Controller
The memory controller interfaces with memory to provide data movement to and from
DRAM along the AIOC-direct and coherent paths to memory. The memory controller is
designed to conform to the IMCH first and next error handling architecture that Section
5.3.1, “Overview of the First and Next Error Architecture” on page 141 describes. The
memory controller reports its unit-level first/next error events through the DRAM_FERR
and DRAM_NERR registers in the memory controller (see Section 11.5, “Error
Handling”). The flow of memory controller errors matches the IMCH behavior for its
other errors as Section 5.3.1 describes.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
153