EP80579 Datasheet, PDF (1085/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-32. Causes of Wake Events
Cause
States can
wake from:
How Enabled
RTC Alarm
S1,S3,S4,S5
Set RTC_EN bit in PM1_EN Register
Power Button
S1,S3,S4,S5
Always enabled as Wake event
GPI[0:15]
S1,S3,S4,S5
GPE0_EN register (after having gone to S5 via SLP_EN, but not after
a power failure.) GPIs that are in the core well are not capable of
waking the system from sleep states where the core well is not
powered.
Classic USB
S1
Set USB1_EN bits in GPE0_EN Register
RI
S1,S3,S4,S5
Set RI_EN bit in GPE0_EN Register
Primary PME#
S1,S3,S4,S5
(Note 2)
PME_B0_EN bit in GPE0_EN register
Secondary PME#
(pin)
S1,S3,S4,S5
(Note 2)
PME_EN bit in GPE0_EN register.
SMBus ALERT#
Signal
S1,S3,S4,S5
Always Enabled as a Wake Event
SMBus Slave
Message
S1,S3,S4,S5,
including S5-
Power Button
Override
Three SMBus commands always enabled as Wake events. These
commands (see Note 1. below) can wake from S5 due to Power
Button.
SMBus Host Notify
message received
S1,S3,S4,S5
HOST_NOTIFY_WKEN bit SMBus Slave Command register.
Reported in the SMB_WAK_STS bit in GPE0_STS register.
Notes:
1.
If in the S5 state due to a powerbutton override or THRMTRIP#, the only wake events are Power
Button, Wake SMBus Slave Message (01h), and Hard Reset SMBus Slave Messages (03h, 04h).
2.
PME#, RTC, GPI[0:n], and RI# will be wake events from S5 only if it was entered via software setting
the SLP_EN and SLP_TYP bits, or if there is a power failure.
3.
GbE wake-up capability (Wake on LAN) is described in Section 37.5.10, “Wake on LAN” on page 1402
4.
There is no support for wake from USB when in S3/S4/S5.
Table 27-33. GPI Wake Events
GPI
GPI[12, 11,
7:0]
GPI[8]
Power Well
Core
Resume
Wake From
Notes
S1
ACPI Compliant
S1,S3,S4,S5 ACPI Compliant
The latency to exit the various sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to CMI are insignificant.
27.6.4
Sx-G3-Sx, Handling Power Failures
In systems, power failures can occur if the AC power is cut (a real power failure) or if
the system is unplugged. In either case, PWROK and RSMRST# are assumed to go low.
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.The AFTER_G3 bit provides the ability to
program whether or not the system should boot once power returns after a power loss
event. If the policy is to not boot, the system remains in an S5 state. There are only
three possible events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When CMI exits G3 after power returns
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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