EP80579 Datasheet, PDF (1672/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

42.3
Block Diagram
Figure 42-1. Expansion Bus Controller
Intel^® EP80579 Integrated Processor
Interface
42.4
42.4.1
Theory of Operation
The Expansion bus controller supports outbound transfers that are initiated by the
EP80579 that target Expansion bus slaves. The Expansion data bus is 16 bits wide and
the address bus is 25 bits wide.
Since the Expansion bus controller has only 1 outbound transaction queue, outbound
accesses all complete in order.
Outbound Transfers
For outbound data transfers, the Expansion bus controller occupies up to 256 Mbytes of
address space in the EP80579’s memory map (refer to signal EX_ADDR [24:0] in
Table 48-24, “Expansion Bus Signals”) and contains a 1-deep address queue, an 8-
word write data fifo, and an 8-word read data FIFO. Eight chip selects are supported to
allow up to eight independent external devices to be connected. The address space for
each chip select is up to 32 Mbytes.
An external clock input, EX_CLK, is required to operate the Expansion interface. The
maximum clock frequency supported by the Expansion bus controller is 80 MHz. The
clock input is provided to allow a wide variety of different peripherals to be connected
to the Expansion interface.To provide a glue-less interface to a wide variety of devices,
the Expansion bus controller supplies eight chips selects to a 16-bit wide external bus,
which can be configured as Intel, Synchronous Intel, Micron ZBT, Motorola, or HPI-style
controls. The signaling characteristics and timing for each chip select is individually
programmable.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1672
August 2009
Order Number: 320066-003US