EP80579 Datasheet, PDF (589/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-212.Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register (Sheet 2
of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 144h
Offset End: 147h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 144h
Offset End: 147h
Size: 32 bit
Default: 0000E000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
SMBCLTO Reporting Mask]:
02
SMBCLTORM 0 = Enable SMBCLTO reporting.
1 = Disable SMBCLTO reporting.
UESMBN Reporting Mask :
01
UESMBNRM 0 = Enable UESMBN reporting.
1 = Disable UESMBN reporting.
SMBLA Reporting Mask :
00
SMBLARM 0 = Enable SMBLA reporting.
1 = Disable SMBLA reporting.
Sticky
Bit Reset
Value
Bit Access
Y
0b
RW
Y
0b
RW
Y
0b
RW
16.4.1.74 Offset 148h: PEAERRDOCMD - PCI Express* Error Do
Command Register
This register supports PCI Express* error commands for doing various signaling.
DO_SCI, DO_SMI, and DO_MCERR, DO_SERR must further be enabled by the PCI
Express* Host Do Command register.
Table 16-213.Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register
(Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 148h
Offset End: 14Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 148h
Offset End: 14Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 29
28 : 24
23 : 21
20 : 16
Bit Acronym
Bit Description
Sticky
Reserved Reserved
First Error Pointer for unmasked PCI Express*
correctable errorsThis pointer is rearmed when all
FEPUPCE unmasked errors have been cleared. In the event of
Y
simultaneous errors, the pointer indicates the least
significant bit of the group. These bits are sticky.
Reserved Reserved
FEPPE
First Error Pointer for PCI Express*-unit errors This
pointer is locked once any units errors are logged in the
PEAFERR. It is rearmed when all PEAUNIT errors have been
cleared. In the event of simultaneous errors, the pointer
Y
indicates the least significant bit of the group. This pointer
is only valid for an error that is enabled for reporting.
These bits are sticky.
Bit Reset
Value
000b
00h
000b
00h
Bit Access
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
589