EP80579 Datasheet, PDF (530/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.5
Offset 06h: PCISTS - PCI Status Register
PCISTS is a 16-bit status register that reports the occurrence of error conditions
associated with the primary side of the “virtual” PCI-PCI bridge embedded within the
IMCH.
Table 16-144.Offset 06h: PCISTS - PCI Status Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 06h
Offset End: 07h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0010h
Power Well: Core
Bit Range
15
14
13
12
11
10 : 09
08
07
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMAS
RTAS
STAS
DEVT
DPD
FB2B
Detected Parity Error: Parity is supported on the primary
side of this device. Since the parity is not checked on the
downstream side from the core, this bit can never be set.
0 = No Parity Error detected
Signaled System Error: Indicates whether or not a NSI
SERR message was generated by this device. For the root
port the fatal and non-fatal messages can be either
received or virtual messages that are forwarded for
reporting.
0 = SERR message not generated by this device.
1 = This device was the source of fatal or non-fatal error
that has been enabled for generation of a System
Error.
Software clears this bit by writing a ‘1’ to the bit location.
Received Master Abort Status: Indicates whether or not
this PCI Express* device received a completion with
Unsupported Request Completion status.
0 = No Master Abort received. Software clears this bit by
writing a ‘1’ to the bit location.
1 = Set when this PCI Express* device receives a
completion with Unsupported Request Completion
Status.
0 = Received Target Abort Status: Indicates whether
or not this PCI Express* device received a completion
with Completer Abort Completion Status. No Target
Abort received. Software clears this bit by writing a ‘1’
to the bit location.
1 = Set when this PCI Express* device receives a
completion with Completer Abort Completion Status.
Signaled Target Abort Status: Not applicable to the
primary side.
0 = This PCI Express* device has not completed a request
using Completer Abort Completion Status.
1 = This PCI Express* device completed a request using
Completer Abort Completion Status.
DEVSEL# Timing: Not Applicable. Hardwired to 0.
0 = Master Data Parity Error Detected: Parity is
supported on the primary side of this device. No
Master Parity Error detected. Software clears this bit
by writing a ‘1’ to the bit location.
1 = Set when this PCI Express* device receives a
completion marked poisoned, or when this device
poisons a write Request. This bit can only be set if the
Parity Error Enable bit is set.
Fast Back-to-Back: Not Applicable
Bit Reset
Value
0b
0b
0b
0b
0b
00b
0b
0b
Bit Access
RO
RWC
RWC
RWC
RO
RO
RWC
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
530
August 2009
Order Number: 320066-003US