EP80579 Datasheet, PDF (71/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

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Summary of Enables for SMBus Slave Write, and SMBus Host Events ...................... 929
Summary of Enables for the Host Notify Command ............................................... 930
Bus 0, Device 31, Function 3, Slave PCI Registers Mapped Through SM_Base (IO) .... 930
Offset 09h: RSA: Receive Slave Address Register ............................................... 931
Offset 0Ah: SD: Slave Data Register ................................................................. 931
Offset 10h: SSTS: Slave Status Register ............................................................ 932
Offset 11h: SCMD: Slave Command Register ..................................................... 932
Offset 14h: NDA: Notify Device Address Register ................................................ 933
Offset 16h: NDLB: Notify Data Low Byte Register ............................................... 934
Offset 17h: NDHB: Notify Data High Byte Register .............................................. 934
Slave Write Cycle Format .................................................................................. 935
Slave Write Registers........................................................................................ 936
Command Types ............................................................................................. 936
Slave Read Cycle Format................................................................................... 937
Data Values for Slave Read Registers ................................................................. 937
Host Notify Protocol ......................................................................................... 939
Bus 0, Device 29, Functions 0, Summary of USB (1.1) Controller PCI Configuration
Registers ........................................................................................................ 941
ID - Identifiers Register ................................................................................... 942
PCICMD - Command Register ........................................................................... 942
PCISTS - Device Status Register ....................................................................... 943
RID - Revision ID Register ............................................................................... 944
SUBC - Sub Class Code Register ....................................................................... 945
BCC - Base Class Code Register ....................................................................... 945
MLT - Master Latency Timer Register ................................................................ 945
HDR - Header Type Register ............................................................................ 946
USBIOBAR - Base Address Register ................................................................... 946
USBx_SVID - USB Subsystem Vendor ID Register ............................................... 947
USBx_SID - USB Subsystem ID Register ........................................................... 947
INTL - Interrupt Line Register .......................................................................... 948
INTP - Interrupt Pin Register ............................................................................ 948
SBRN - Serial Bus Release Number Register ....................................................... 948
USBLKMCR - USB Legacy Keyboard/Mouse Control Register ................................. 949
USBREN - USB Resume Enable Register ............................................................ 951
USBCWP - USB Core Well Policy Register ........................................................... 951
MANID - Manufacturer ID Register .................................................................... 952
Summary of USB (1.1) Controller Configuration Registers Mapped Through
USBIOBAR I/O BAR .......................................................................................... 953
USBCMD: USB Command Register .................................................................... 954
Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation............ 956
USBSTS: USB Status Register .......................................................................... 957
USBINTR: USB Interrupt Enable Register ........................................................... 959
FRNUM: Frame Number Register ...................................................................... 959
FRBASEADD: Frame List Base Address Register .................................................. 960
SOFMOD: Start of Frame Modify Register .......................................................... 961
PSCR - Port Status and Control Register ............................................................ 962
Queue Advance Criteria..................................................................................... 968
USB Schedule List Traversal Decision Table ......................................................... 969
Data Field ....................................................................................................... 971
Bits Maintained in Low Power States ................................................................... 975
USB Legacy Keyboard/Mouse Control Register Bit Implementation ......................... 975
USB 1.1 and USB 2.0 Comparison ..................................................................... 977
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI Configuration
Registers ........................................................................................................ 978
Offset 00h: VID - Vendor ID Register ................................................................ 979
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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