EP80579 Datasheet, PDF (23/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
23.1.3.2 Offset 72h: PC – PCI Power Management Capabilities Register .............. 834
23.1.3.3 Offset 74h: PMCS – PCI Power Management Control And
Status Register............................................................................... 835
23.1.4 Message Signaled Interrupt Capability ...................................................... 836
23.1.4.1 Offset 80h: MID – Message Signaled Interrupt Identifiers Register ........ 836
23.1.4.2 Offset 82h: MC – Message Signaled Interrupt Message
Control Register.............................................................................. 837
23.1.4.3 Offset 84h: MA – Message Signaled Interrupt Message
Address Register............................................................................. 838
23.1.4.4 Offset 88h: MD – Message Signaled Interrupt Message
Data Register ................................................................................. 838
23.1.5 Additional Configuration Registers ............................................................ 838
23.1.5.1 Offset 90h: MAP – Port Mapping Register ........................................... 839
23.1.5.2 Offset 92h: PCS – Port Control and Status Register ............................. 839
23.1.6 Serial ATA Capability Registers................................................................. 841
23.1.6.1 Offset A8h: SATACR0 – Serial ATA Capability Register 0....................... 841
23.1.6.2 Offset ACh: SATACR1 – Serial ATA Capability Register 1 ...................... 841
23.1.7 Additional Configuration Registers ............................................................ 842
23.1.7.1 Offset C0h: ATC – APM Trapping Control Register................................ 842
23.1.7.2 Offset C4h: ATS – ATM Trapping Status Register................................. 843
23.1.7.3 Offset D0h: SP – Scratch Pad Register ............................................... 844
23.1.7.4 Offset E0h: BFCS – BIST FIS Control/Status Register........................... 844
23.1.7.5 Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register....................... 846
23.1.7.6 Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register....................... 846
23.1.7.7 Offset F8h: MANID – Manufacturing ID Register .................................. 847
23.2 SATA I/O Mapped Registers .............................................................................. 847
23.2.1 Primary Devices ..................................................................................... 848
23.2.1.1 Offset 00h: PCMD – Primary Command Register ................................. 848
23.2.1.2 Offset 02h: PSTS – Primary Status Register........................................ 849
23.2.1.3 Offset 04h: PDTP – Primary Descriptor Table Pointer Register ............... 849
23.2.2 Secondary Devices ................................................................................. 850
23.2.2.1 Offset 08h: SCMD – Secondary Command Register ............................. 850
23.2.2.2 Offset 0Ah: SSTS – Secondary Status Register ................................... 850
23.2.2.3 Offset 0Ch: SDTP – Secondary Descriptor Table Pointer Register ........... 850
23.2.3 AHCI Index and Data Registers ................................................................ 850
23.2.3.1 Offset 10h: INDEX – AHCI Index Register .......................................... 850
23.2.3.2 Offset 14h: DATA – AHCI Data Register ............................................. 851
23.3 SATA Memory Mapped Registers ....................................................................... 851
23.3.1 Generic Host Controller ........................................................................... 852
23.3.1.1 Offset 00h: HCAP – HBA Capabilities Register ..................................... 853
23.3.1.2 Offset 04h: GHC – Global HBA Control Register................................... 855
23.3.1.3 Offset 08h: IS – Interrupt Status Register .......................................... 856
23.3.1.4 Offset 0Ch: PI – Ports Implemented Register ...................................... 856
23.3.1.5 Offset 10h: VS – AHCI Version Register ............................................. 857
23.3.2 Vendor Specific Registers ........................................................................ 857
23.3.2.1 Offset A0h: SGPO - SPGIO Control Register........................................ 857
23.3.3 Port DMA Registers................................................................................. 858
23.3.3.1 Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register..
858
23.3.3.2 Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Upper 32-
bits Register................................................................................... 858
23.3.3.3 Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register............. 859
23.3.3.4 Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits
Register ........................................................................................ 859
23.3.3.5 Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register ............... 860
23.3.3.6 Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register............... 861
23.3.3.7 Offset 118h: PxCMD[0-1] – Port [0-1] Command Register.................... 863
23.3.4 Port Interface Registers (One Set Per Port) ................................................ 866
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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