EP80579 Datasheet, PDF (342/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.11.2
12.11.3
4. Clear the Channel Status Register (CSR) of any asserted error or status bits. Each
EDMA channel will not initiate a new transfer when an error condition remains in
the CSR.
5. Clear the Suspend bit and set the Start bit in the Channel Control Register (CCR).
Since this is the start of a new transfer and not the resumption of a previous
transfer, the Channel Resume bit in the CCR must be clear. (Resume overrides
start.)
6. The channel starts the transfer by fetching the chain descriptor at the address
contained in the Next Descriptor Address Register (NDAR/NDUAR). The channel
moves the NDAR/NDUAR values into the CDAR/CDUAR, and loads the chain
descriptor values into their corresponding internal registers. If the load completes
without any error, the actual data transfer begins. The Current Descriptor Address
Register (CDAR/CDUAR) now contains the address of the chain descriptor just
fetched and the Next Descriptor Address Register (NDAR/NDUAR) now contains the
descriptor address of the next descriptor in the chain, if any.
7. When the current EDMA transfer has completed without any errors, the channel
fetches the next chain descriptor from the address contained in the Next Descriptor
Address Register (NDAR/NDUAR) automatically without any software intervention,
and proceeds with the next block transfer (provided the value in the NDAR/NDUAR
pair is non-zero).
The last descriptor in the chain list has a null value in the Next Descriptor Address field,
specifying the end of the chain. The null value in the Next Descriptor Address Register
(NDAR/NDUAR) notifies the channel not to read additional chain descriptors from local
system memory, and the channel goes idle.
Suspend Function
Software may temporarily suspend execution of a descriptor chain by setting the
Suspend bit in the Channel Control Register (CCR). The target channel will complete
execution of the current descriptor and suspend operation without losing current
status. Software may later cause the channel to resume execution of the descriptor
chain by writing to the CCR to clear the Suspend bit and set the Resume bit. In
response, the channel will initiate a descriptor fetch from the NDAR/NDUAR, and
resume the suspended operation.
Software does not need to re-program the channel configuration after a suspend
sequence.
Stop Function
Software may intentionally abort a transfer by setting the Stop bit in the Channel
Control Register (CSR). Once aborted, the transfer cannot be resumed. In response to
the Stop bit, the target channel will immediately cease fetching source data, drain any
buffered destination data, and go idle. Usage of this mechanism will result in assertion
of the Stopped status bit in the CSR, and will generate an interrupt if so enabled. (Note
that the stop function is sufficiently fast in the IMCH that reading back the channel
status register is preferred over utilizing the interrupt on stop function.)
Usage of the Stop mechanism will not result in assertion of the Abort status bit, nor will
it generate an “interrupt on abort” indication if so enabled. The channel differentiates
an abort on error from an abort on software command, and will ensure that all error
status bits remain clear.
If the MSI mechanism is in use for interrupt generation, and independent messages are
defined for abort on error and normal run-time interrupts, the latter message type will
be utilized on behalf of the stop function.
Intel^® EP80579 Integrated Processor Product Line Datasheet
342
August 2009
Order Number: 320066-003US