EP80579 Datasheet, PDF (385/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.3.4
Device and Slot Power Limits
All add-in devices must power-on to a state in which they limit their total power
dissipation to a default maximum according to their form-factor (10 W for add-in edge-
connected cards). When BIOS updates the slot power limit register of the root ports
within the IMCH, the IMCH automatically transmits a Set_Slot_Power_Limit message
with corresponding information to the attached device.The platform BIOS is responsible
for properly configuring the slot power limit registers in the IMCH. Failure to do so may
result in attached endpoints remaining completely disabled in order to comply with the
default power limitations associated with their form-factors.
15.3.5
PME Support
All information in this section refers to the IMCH PME support. See Chapter 27.0,
“Power Management” for PME support in IICH.
In CMI systems, only the system power manager or a device within the PCI Express
hierarchy may initiate a power state change. Thus the only Power Management Event
(PME) signaling support required in the IMCH is that associated with PCI Express. Note
that a device bridging to another technology, such as a PXH bridging to PCI-X, may
convert traditional PME signaling into PCI Express in-band PME messaging and thereby
meet this requirement of the IMCH.
PME signaling in PCI Express is crafted to accomplish two distinct functions. First, it
provides a signaling mechanism for devices requiring service to propagate a wake-up
request to the power management controller. Second, it provides a messaging
mechanism for devices requesting a power state change to pass their unique location
within the PCI Express hierarchy to the power management controller. The combination
of these two functions provides great flexibility and controllability for the power
manager.
15.3.5.1 PME Wake Signaling
Wake signaling is only required to provide for device-initiated transition out of low
power states where clock and/or power have been removed from the sleeping device.
The PME mechanism does not require a wake-up function for attached devices still
powered and receiving an interface reference clock, as devices in this state may simply
initiate PME messaging directly. Wake is only required if the device wishing to initiate a
PME message cannot do so without first requesting a change to the system clocking
and power profile from the power management controller.
The wake signaling aspect of the system power management solution may vary in
elegance and granularity. Depending upon the support level provided by the power
management controller, a wake-up request from any given device may cause power
and clocking to be restored to the entire system, to just the affected branch of the PCI
Express hierarchy, or only to the requesting device.
While the PCI Express Interface Specification provides for two distinct wake signaling
mechanisms, CMI supports only the legacy mechanism described below.
15.3.5.1.1 Legacy Wake Mechanism
The legacy wake signaling mechanism is analogous to that used in historical PCI-based
system designs. In this case, the platform architect is responsible for crafting paths
routing collected wake signals between wake-capable devices and the management
controller without participation from the IMCH and IICH equivalent devices. The
collection of wake logic must run on auxiliary power, and must comprehend the
potential for devices both with and without supplied auxiliary power co-existing on the
same branch of the PCI Express hierarchy. Refer to the PCI Express Interface
Specification for further details on legacy wake signaling.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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