EP80579 Datasheet, PDF (1112/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
29.4
Warning:
Update Cycles
An update cycle occurs once a second, if the SET bit of register B is not asserted and
the divide chain is properly configured. During this procedure, the stored time and date
are incremented, overflow is checked, a matching alarm condition is checked, and the
time and date are rewritten to the RAM locations. The update cycle will start at least
488 μs after the UIP bit of register A is asserted, and the entire cycle will not take more
than 1984 μs to complete. The time and date RAM locations (0–9) is disconnected from
the external bus during this time.
To avoid update and data corruption conditions, external RAM access to these locations
can safely occur upon the detection of either of two conditions.
1. When an updated-ended interrupt is detected, almost 999 ms is available to read
and write the valid time and date data.
2. If the UIP bit of Register A is detected to be low, there is at least 488 μs before the
update cycle begins.
The overflow conditions for leap years and daylight savings adjustments are based on
more than one date or time item. To ensure proper operation when adjusting the time,
the new time and data values should be set at least two seconds before one of these
conditions (leap year, daylight savings time adjustments) occurs.
29.5
Interrupts
The real-time clock interrupt is internally routed within the IICH both to the I/O APIC
and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the IICH
prior to connection to the interrupt controller, nor is it shared with any other interrupt.
IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event
Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked.
29.6
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the
PCI configuration space. If the locking bit is set, the corresponding range in the RAM is
not readable or writeable. A write cycle to those locations has no effect. A read cycle to
those locations does not return the locations actual value (resultant value is
undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will
invoke the BIOS and allow it to relock the RAM range.
29.7
Century Rollover
The IICH detects a roll over when the Year byte (RTC I/O space, index offset 09h)
transitions from 99 to 00 (e.g., a rollover from December 31, 2099, 11:59:59 p.m. to
12:00:00 a.m on January 1^st, 2100). Upon detecting the rollover, the IICH sets the
NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this
causes an SMI#. The SMI# handler can update registers in the RTC RAM that are
associated with the century value.
If the system is in a sleep state (S3 and S5) when the century rollover occurs, the IICH
also sets the NEWCENTURY_STS bit, but no SMI# is generated. When the system
resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and
update the century value in the RTC RAM.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1112
August 2009
Order Number: 320066-003US