EP80579 Datasheet, PDF (1448/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.6 EEPROM_RR – EEPROM Read Register
Table 37-30. EEPROM_RR – EEPROM Read Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0014h
Offset End: 0017h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0014h
Offset End: 0017h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0014h
Offset End: 0017h
Size: 32 bits
Default: XXXXXX00h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 16
15 : 08
07 : 05
04
03 : 01
00
Bit Acronym
Bit Description
Sticky
DATA
ADDR
RSVD
DONE
RSVD
START
Read Data
Data returned from the EEPROM read.
Read Address
This field is written by software along with Start Read to
indicate the word to read.
Reserved
Reads as 0
Read Done
Set to 1 when the EEPROM read completes.
Set to 0 when the EEPROM read is in progress.
Writes by software are ignored.
Reserved
Reads as 0
Start Read
Writing a 1 to this bit causes the EEPROM to read a (16-bit)
word at the address stored in the EE_ADDR field, storing
the result in the EE_DATA field. This bit is self-clearing
Bit Reset
Value
X
X
0h
0h
0h
0h
Bit Access
RO
RW
RV
RO
RV
RW
Note:
This registers is used by software to read individual words in the EEPROM. To read a
word, software writes the address to the Read Address field and simultaneously writes
a 1 to the Start Read field. The GbE will read the word from the EEPROM and place it in
the Read Data field, setting the Read Done filed to 1. Software can poll this register,
looking for a 1 in the Read Done filed, and then using the value in the Read Data field.
When this register is used to read a word from the EEPROM, that word is not written to
any of the MAC's internal registers even if it is normally a hardware accessed word.
If SW has requested direct pin control of the EEPROM using the EEC register, an access
through the EERD register mechanism may stall until the EEC control has been
released. SW should ensure that EEC.EE_REQ=0 and that EEC.EE_GNT=0 as well
before attempting to utilize EERD to access the EEPROM.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1448
August 2009
Order Number: 320066-003US