EP80579 Datasheet, PDF (1500/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.10 TXDCTL – Transmit Descriptor Control Register
This register controls the fetching and write-back of transmit descriptors. The three
threshold values are used to determine when descriptors will be read from and written
to host memory. The values may be in units of cache lines or 16B descriptors.
Table 37-76. TXDCTL: Transmit Descriptor Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3828h
Offset End: 382Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3828h
Offset End: 382Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3828h
Offset End: 382Bh
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
31 : 25
24
23 : 22
Bit Acronym
Bit Description
Sticky
LWTHRESH
GRAN
Rsvd
Transmit Descriptor Low Threshold. This field controls
the number of pre-fetched transmit descriptors at which a
transmit descriptor-low interrupt is reported. Asserting
ICR.TXD_LOW only when the processing distance from the
TDT register drops below LWTHRESH may allow software to
operate more efficiently by maintaining a continuous
addition of transmit work, interrupting only when the
hardware nears completion of all submitted work.
An interrupt condition is asserted when the number of
descriptors available transitions from
threshold_level + 1 -> threshold_level
where LWTHRESH specifies a multiple of 8 descriptors, (i.e.
threshold_level = 8*LWTHRESH).
Setting this value to 0 will cause this interrupt to be
generated only when the transmit descriptor cache
becomes completely empty.
Granularity of the thresholds in this register.
0 = Cache Lines
1 = Descriptors (16B each)
Reserved
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1500
August 2009
Order Number: 320066-003US