EP80579 Datasheet, PDF (214/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-27. Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
92h
A8h
ACh
C0h
C4h
D0h
E0h
E4h
E8h
F8h
92h
ABh
AFh
C0h
C4h
D3h
E3h
E7h
EBh
FBh
“Offset 92h: PCS – Port Control and Status Register” on page 840
“Offset A8h: SATACR0 – Serial ATA Capability Register 0” on page 841
“Offset ACh: SATACR1 – Serial ATA Capability Register 1” on page 841
“Offset C0h: ATC – APM Trapping Control Register” on page 842
“Offset C4h: ATS – ATM Trapping Status Register” on page 843
“Offset D0h: SP – Scratch Pad Register” on page 844
“Offset E0h: BFCS – BIST FIS Control/Status Register” on page 844
“Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register” on page 846
“Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register” on page 846
“Offset F8h: MANID – Manufacturing ID Register” on page 847
Default
Value
00h
00100012h
00000048h
00h
00h
00000000h
00000000h
00000000h
0h
Variable
Table 7-28. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through LBAR I/O BAR
Offset Start Offset End
Register ID - Description
00h
00h
“Offset 00h: PCMD – Primary Command Register” on page 848
02h
02h
“Offset 02h: PSTS – Primary Status Register” on page 849
04h
07h
“Offset 04h: PDTP – Primary Descriptor Table Pointer Register” on page 849
10h
13h
“Offset 10h: INDEX – AHCI Index Register” on page 850
14h
17h
“Offset 14h: DATA – AHCI Data Register” on page 851
Default
Value
00h
00h
Variable
00000000h
Variable
Table 7-29. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through ABAR Memory BAR (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
04h
08h
0Ch
10h
A0h
100h, 180h
104h, 184h
108h, 188h
03h
07h
0Bh
0Fh
13h
A3h
17Fh, 1FFh
107h, 187h
10Bh, 18Bh
“Offset 00h: HCAP – HBA Capabilities Register” on page 853
Variable
“Offset 04h: GHC – Global HBA Control Register” on page 855
00000000h
“Offset 08h: IS – Interrupt Status Register” on page 856
00000000h
“Offset 0Ch: PI – Ports Implemented Register” on page 856
00000000h
“Offset 10h: VS – AHCI Version Register” on page 857
00010100h
“Offset A0h: SGPO -SPGIO Control Register” on page 857
00000000h
“Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register” on
page 858
Variable
“Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register” on
page 858
Variable
“Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register” on page 859
Variable
Intel^® EP80579 Integrated Processor Product Line Datasheet
214
August 2009
Order Number: 320066-003US