EP80579 Datasheet, PDF (1212/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-41. Logical Device 6 (Watch Dog Timer)
Logical Device Register
Address
Description
Enable
Default = 00h
I/O Base Address
Default = 00h
Primary Interrupt
Select
Default = 00h
30h
(RW)
60h
(RW)
61h
(Bits 7:5 RW
Bits 4:0 RO)
70h
(RW)
Bits[7:1] Reserved, set to zero.
Bit[0]
1 =enable the logical device currently selected through the
Logical Device # register.
0 =Logical device currently selected is inactive
Registers 60h (MSB) and 61h (LSB) set the base address for the
device. Note: Decode is on 32 Byte boundaries.
WDT Base Address is generated by using the LPC Generic
Decode Range 1 register (LG1), see D31:F0:84h for more
details. This Base Address must be within the 128 bytes of LG1
Base register. Also the last byte accessed by the WDT must not
exceed the LG1 Base Address +128 bytes.
Bits[3:0] selects which interrupt level is used for the primary
Interrupt.
00= no interrupt selected
01= IRQ1
02= IRQ2
03= IRQ3
04= IRQ4
05= IRQ5
06= IRQ6
07= IRQ7
08= IRQ8
09= IRQ9
0A= IRQ10
0B= IRQ11
0C= IRQ12
0D= IRQ13
0E= IRQ14
0F= IRQ15
Bits[7:4] Reserved
Note: An Interrupt is activated by enabling this device (offset
30h), setting this register to a non-zero value and when
the first stage has been allowed to reach zero. An
Interrupt is not generated if WDT_TOUT_CNF is set to
change output after every timeout (See WDT Lock
Register).
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Intel^® EP80579 Integrated Processor Product Line Datasheet
1212
August 2009
Order Number: 320066-003US