EP80579 Datasheet, PDF (1141/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 30-28. APIC_RTE[0-39] - Redirection Table Entry (Sheet 3 of 3)
Description:
Offset: vector 0: 10h-11h, vector
Hex)) -(11h + (N*2 in Hex))
1:
12h-13h,
vector
23:
3Eh-3Fh,
vector
39:
5Eh-5Fh;
vector
N:
(10h+
(N*2
in
View: IA I
Win:Idx: APIC_WDW:APIC_IDX
Vector 0
10h at 02h
Offset Start: (4B)
Offset End: 11h at 02h
(4B)
Size: 64 bit^a
Default: XXXX00000001XXXXh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
11
10 : 08
07 : 00
DSM
DLM
VCT
Destination Mode: This field determines the
interpretation of the Destination field.
0 = Physical. Destination APIC ID is identified by bits
59:56.
1 = Logical. Destinations are identified by matching bit
63:56 with the Logical Destination in the
Destination Format Register and Logical
Destination Register in each Local APIC.
Delivery Mode: This field specifies how the APICs
listed in the destination field must act upon reception of
this signal. Delivery Modes will only operate as
intended when used in conjunction with a specific
trigger mode. The encodings are:
000 Fixed: Deliver the signal on the INTR signal of all
processor cores listed in the destination. Trigger Mode
can be edge or level.
001 Lowest Priority: Deliver the signal on the INTR
signal of the processor core that is executing at the
lowest priority among all the processors listed in the
specified destination. Trigger Mode can be edge or
level.
010 SMI: Not supported. Requires the interrupt to be
programmed as edge triggered.
011 Rreserved
100 NMI: Not supported.
101 INIT: Not supported.
110 Reserved
111 ExtINT: Deliver the signal to the INTR signal of
all processor cores listed in the destination as an
interrupt that originated in an externally connected
8259A compatible interrupt controller. The INTA cycle
that corresponds to this ExtINT delivery is routed to the
external controller that is expected to supply the vector.
Requires the interrupt to be programmed as edge
triggered.
Vector: This field contains the interrupt vector for this
interrupt. Values range between 10h and FEh.
a. 64 bit each, accessed as two 32 bit quantities
Bit Reset
Value
X
X
X
Bit Access
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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