EP80579 Datasheet, PDF (986/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.12 Offset 2Eh: SSID - USB 2.0 Subsystem ID Register
Table 26-14. Offset 2Eh: SSID - USB 2.0 Subsystem ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: XXXXh
Power Well: Core
Bit Range
15 :00
Bit Acronym
Bit Description
Sticky
SSID
BIOS sets the value in this register to identify the
Subsystem ID. This register, in combination with the
Subsystem Vendor ID register, enables the operating
system to distinguish each subsystem from other(s).
Writes to this register are enabled when the WRT_RDONLY
bit (offset 80h, bit 0) is set to 1. Writes must be done as a
single 16-bit cycle.
Bit Reset
Value
XXXXh
Bit Access
RW
26.2.1.13 Offset 34h: CAP_PTR - Capabilities Pointer Register
Table 26-15. Offset 34h: CAP_PTR - Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: 50h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
CAP_PTR
This register points to the starting offset of the USB 2.0
capabilities ranges.
Bit Reset
Value
50h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
986
August 2009
Order Number: 320066-003US