EP80579 Datasheet, PDF (1749/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 48-12. IICH Interrupt Signals (Sheet 2 of 2)
Signal Name
GP2_PIRQE#
SERIRQ
IO Type
LVTTL,3.3V
TOTAL
Direction
Ball
Count
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
See GPIO interface.
I
1
10K Up (in
PIRQ
BSC
Serial Interrupt Request: This pin implements
the serial interrupt protocol.
mode)
This signal is not 5V tolerant. It is 3.3 V tolerant.
1
48.4.3.3 Serial Peripheral Interface (SPI)¹
Table 48-13. SPI Interface Signals
Signal Name
IO Type
Direction
Ball
Count
SPI_SCLK
LVTTL,3.3V
O
1
SPI_CS#
LVTTL,3.3V
O
1
SPI_MOSI
LVTTL,3.3V
O
1
SPI_MISO
LVTTL,3.3V
I
1
TOTAL
4
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/
Alternate Mode
BSC
BSC
BSC
BSC
Serial bit-rate Clock
CS for Slave
Master data out/Slave In
Master data in/Slave out
48.4.3.4 Low Pin Count (LPC) Interface
Table 48-14. LPC and FWH Interface Signals (Sheet 1 of 2)
Signal Name
LAD[3:0]
LFRAME#
GP41_LDRQ[1]#
IO Type
LVTTL,3.3V
LVTTL,3.3V
Direction
Ball
Count
I/O
4
O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
LPC Multiplexed Command, Address, Data
LAD[3:0] may be used as Firmware Hub [3:0]
signals.
LPC Frame: LFRAME# Indicates the start of an
LPC cycle, or an abort.
LFRAME# may be used as Firmware Hub [4]
signal.
See GPIO interface.
1. Intel recommends using the SPI for Pre-boot firmware due to the reduced availability of LPC FWH.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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