EP80579 Datasheet, PDF (867/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-64. Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register (Sheet 2 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 120h, 1A0h
Offset End: 123h, 1A3h
Size: 32 bit
Default: 0000007Fh
Power Well: Core
Bit Range
15 : 08
Bit Acronym
Bit Description
ERR
Error (ERR): Contains the latest copy of the task file
error register.
Status (STS): Contains the latest copy of the task file
status register. Fields of note in this register that affect
AHCI:
Sticky
Bit Reset
Value
Bit Access
0h
RO
07 : 00
STS
Bit
Field Definition
7
BSY Indicates the interface is busy
6:4
N/A Not applicable
3
DRQ
Indicates a data transfer is
requested
2:1
N/A Not applicable
0
ERR
Indicates an error during the
transfer.
Note that the HBA updates all 8 bits of this register from
the received FIS, not just the bits noted above.
7Fh
RO
23.3.4.2
Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
Table 23-65. Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 124h, 1A4h
Offset End: 127h, 1A7h
Size: 32 bit
Default: FFFFFFFFh
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Signature (SIG): Contains the signature received from a
device on the first D2H register FIS. The bit order is as
follows:
Bit Reset
Value
Bit Access
31 : 00
SIG
Bit
31:24
23:16
15:08
07:00
Field
LBA High Register
LBA Mid Register
LBA Low Register
Sector Count Register
FFFFFFFFh
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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