EP80579 Datasheet, PDF (496/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.53 Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct
Syndrome Register
Syndrome for correctable errors occurring in the memory system. The contents of this
register are set when correctable error bit (bit 0) is set in the DRAM_FERR register (see
Section 16.2.1.36, “Offset 80h: DRAM_FERR - DRAM First Error Register”). Syndrome
is always logged for QW0/1 or QW2/3 pairs (block), if transferring the lower half of the
cache line, and logged for QW4/5 or QW6/7 if transferring the upper half of the cache
line. ECC is checked ½ cacheline at a time. The syndrome logged in this register is for
the lowest ordered QW pair. For example: If both QW0/1 and QW2/3 have correctable
errors, the syndrome stored is for QW0/1. A syndrome indicates error when it is a non-
zero value. The bits in this register are sticky through reset.
Table 16-107.Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct
Syndrome Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: C4h
Offset End: C5h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :00
Bit Acronym
Bit Description
SECF_SYND
ECC Syndrome for DRAM_FERR correctable error:
Because only hardware writes to this register, it is read-
only.
SEC mode
Bits 15:00 Mem Channel
Sticky
Y
Bit Reset
Value
0000h
Bit Access
RO
16.2.1.54 Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register
Syndrome for next correctable error occurring in the memory system. The contents of
this register are set when correctable error bit (bit 0) is set in the DRAM_NERR register
(see Section 16.2.1.37, “Offset 82h: DRAM_NERR - DRAM Next Error Register”). The
bits in this register are sticky through reset.
Table 16-108.Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: C6h
Offset End: C7h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 :00
SECN_SYND
ECC Syndrome for DRAM_NERR correctable error
indicated by DRAM NERR register: Because only
hardware writes to this register, it is Read-Only.
Details are in Section 16.2.1.53.
Sticky
Bit Reset
Value
Bit Access
Y
0000h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
496
August 2009
Order Number: 320066-003US