EP80579 Datasheet, PDF (879/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.5
23.5.5.1
23.5.5.2
DW
0
Features
1
Dev / Head
2
Features (exp)
3
Control
4
Reserved (0)
Command
Cyl High (52h)
Cyl High Exp (51h)
Reserved (0)
Reserved (0)
C 0000000
Cyl Low (42h)
Cyl Low Exp (41h)
Sector Count Exp (21h)
Reserved (0)
FIS Type (27h)
Sector Number (32h)
Sector Num Exp
(31h)
Sector Count (22h)
Reserved (0)
The writes do not have to come in any specific order. All that is necessary is that the
writes to these registers act as a FIFO – the second write moves data from the first
write into a new location.
There are also special considerations when reading from the task file to support 48-bit
LBA operation. Software may need to read all 16-bits. Since the registers are only 8-
bits wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3f6h for primary and 376h for secondary (or their native counterparts).
If software clears bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
Power Management Operation
Introduction
Power management of the SATA Controller and ports will cover operations of the host
controller and the SATA wire. This specification does not cover any power management
that an SATA device may do internally that is transparent to the interface.
Power State Mappings
The PCI specification defines power management states for devices, which will be
applied to the SATA host controller. They are:
• D0 – working (required).
• D1 – light sleep (not supported).
• D2 – deeper sleep (not supported).
• D3 – very deep sleep (required). This state is split into two sub-states, D3_HOT (can
respond to PCI configuration accesses) and D3_COLD (cannot respond to PCI
configuration accesses). These two sub-states are considered the same, where
D3_HOT has V_CC, but D3_COLD does not. This is the only state allowed for the host
controller when the system is in an S1-S5 state.
SATA devices may also have multiple power states. From parallel ATA, three device
states are supported through ACPI. They are:
• D0 – Device is working and instantly available.
• D1 – device enters when it receives a STANDBY IMMEDIATE command. Exit latency
from this state is in seconds.
• D3 – from the SATA device’s perspective, no different than a D1 state, in that it is
entered via the STANDBY IMMEDIATE command. However, an ACPI method is also
called which will reset the device and then cut its power through proprietary chipset
methods. (In ICH, this included setting the tri-state bits of the interface, a GPIO
which reset the device, and a GPIO to cut power to that device.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
879