EP80579 Datasheet, PDF (20/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
19.2.1.8 Offset 2Ch: SID: Subsystem Identifiers Register.................................. 738
19.2.2 ACPI/GPIO Configuration Registers ........................................................... 738
19.2.2.1 Offset 40h: ABASE: ACPI Base Address Register.................................. 738
19.2.2.2 Offset 44h: ACT: ACPI Control Register .............................................. 739
19.2.2.3 Offset 48h: GBA: GPIO Base Address Register..................................... 740
19.2.2.4 Offset 4Ch: GC: GPIO Control Register ............................................... 741
19.2.3 Interrupt Configuration Registers .............................................................. 741
19.2.3.1 Offset 60h: PARC: PIRQA Routing Control Register .............................. 741
19.2.3.2 Offset 61h: PBRC: PIRQB Routing Control Register .............................. 742
19.2.3.3 Offset 62h: PCRC: PIRQC Routing Control Register .............................. 742
19.2.3.4 Offset 63h: PDRC: PIRQD Routing Control Register .............................. 743
19.2.3.5 Offset 64h: SCNT: Serial IRQ Control Register..................................... 744
19.2.3.6 Offset 68h: PERC: PIRQE Routing Control Register............................... 745
19.2.3.7 Offset 69h: PFRC: PIRQF Routing Control Register ............................... 745
19.2.3.8 Offset 6Ah: PGRC: PIRQG Routing Control Register .............................. 746
19.2.3.9 Offset 6Bh: PHRC: PIRQH Routing Control Register .............................. 747
19.2.4 LPC I/O Configuration Registers................................................................ 747
19.2.4.1 Offset 80h: iOD: i/O Decode Ranges Register...................................... 747
19.2.4.2 Offset 82h: IOE: I/O Enables Register ................................................ 749
19.2.4.3 Offset 84h: LG1: LPC Generic Decode Range 1 Register........................ 750
19.2.4.4 Offset 88h: LG2: LPC Generic Decode Range 2 Register........................ 751
19.2.5 Power Management Configuration Registers ............................................... 751
19.2.6 FWH Configuration Registers .................................................................... 751
19.2.6.1 Offset D0h: FS1: FWH ID Select 1 Register ......................................... 751
19.2.6.2 Offset D4h: FS2: FWH ID Select 2 Register ......................................... 753
19.2.6.3 Offset D8h: FDE: FWH Decode Enable Register.................................... 754
19.2.6.4 Offset DCh: BC: BIOS Control Register............................................... 756
19.2.7 Root Complex Register Block Configuration Register .................................... 756
19.2.7.1 Offset F0h: RCBA: Root Complex Base Address Register ....................... 756
19.2.8 Manufacturing Information Register .......................................................... 757
19.2.8.1 Offset F8h: MANID: Manufacturer ID Register ..................................... 757
19.3 Interface ........................................................................................................ 757
19.3.1 Overview............................................................................................... 758
19.3.2 Cycle Types ........................................................................................... 758
19.3.3 Aborting a Cycle ..................................................................................... 759
19.3.4 Memory Cycle Notes ............................................................................... 759
19.3.5 I/O Cycle Notes ...................................................................................... 760
19.3.6 DMA Cycle Notes .................................................................................... 760
19.3.7 Bus Master Cycle Notes ........................................................................... 760
19.3.8 FWH Cycle Notes .................................................................................... 760
19.3.9 LPC PD# Protocol ................................................................................... 760
19.3.10 Cycle Posting Policies .............................................................................. 760
19.3.11 Configuration ......................................................................................... 761
19.3.11.1 LPC Interface Decoders .................................................................... 761
19.3.11.2 Bus Master Device Mapping and START Fields ..................................... 761
19.3.11.3 Firmware Memory IDSEL fields.......................................................... 761
19.3.12 SERR# Generation ................................................................................. 761
20.0 LPC DMA ................................................................................................................ 763
20.1 Overview ........................................................................................................ 763
20.2 LPC DMA I/O-Mapped Register Details ................................................................ 764
20.2.1 Register Descriptions .............................................................................. 766
20.2.1.1
20.2.1.2
Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for
Channels 0-3 .................................................................................. 766
Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for
Channels 5-7 .................................................................................. 767
Intel^® EP80579 Integrated Processor Product Line Datasheet
20
August 2009
Order Number: 320066-003US