EP80579 Datasheet, PDF (139/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
5.0
5.1
5.2
5.2.1
Error Handling
Overview
This section presents an overview of the error handling mechanisms that the EP80579
provides. The intent of this discussion is to provide a broad background to error
handling on the chip. Register definitions and other error handling details can be found
in the discussions of the relevant units throughout this document.
EP80579 View of Error Reporting
This section describes the guiding principles on which the error logging and reporting
registers are based for the EP80579. For the purposes of this discussion, an “error” is
an exceptional condition that is beyond the control of the EP80579 hardware or
software and might result in data corruption or data loss. This definition does not cover
“functional” errors that are not beyond the control of the EP80579. For example, this
section discusses double-bit ECC errors as they involves data corruption that occurs
through no overt action of the EP80579; it does not cover an underflow error on a ring
since this is a functional condition that can be managed in software to avoid data loss.
Hardware Capabilities
With respect to their error handling capabilities, the blocks on the EP80579 can be
divided into three groups: the IA blocks (including the IA-32 core, IMCH exclusive of
the memory interface, IICH), the memory controller interface, and the AIOC blocks.
Generally speaking,
• The IA blocks (see Section 5.3, “Error Reporting by the IMCH” on page 141 and
Section 5.4, “Error Reporting by the IICH” on page 149) use the FERR/NERR and
PCI error reporting infrastructures.
• The memory controller block (see Section 5.5, “Error Reporting by the System
Memory Controller” on page 153) uses the FERR/NERR error reporting
infrastructure.
• The AIOC blocks (see Section 5.6, “Error Reporting by AIOC Devices” on page 155)
use their existing error reporting infrastructures that are “bridged” into the IA-32
core to report errors to IA through PCI signals (i.e., INTx or MSI depending on
device configuration). These blocks do not support other PCI error reporting
capabilities such as SERR or the IMCH FERR/NERR architecture.
This organization allows an EP80579 system to use standard IA platform reporting
abstractions and algorithms throughout the IA portion of the chip (including the
memory controller). AIOC devices then use PCI INTx or MSI signaling to present their
error handling within the IA infrastructure. Utilizing signaling in this fashion implies that
the responsibility for error handling in AIOC devices resides with Intel provided AIOC
device drivers in the EP80579 software stack.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
139