EP80579 Datasheet, PDF (484/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.37 Offset 82h: DRAM_NERR - DRAM Next Error Register
This register captures the errors related to the DRAM Controller that occur after the
first error is detected and captured in DRAM_FERR. Refer to Section 11.5, “Error
Handling” to understand the error handling mechanism implemented in the memory
controller.
Multiple bits can be set in this register if multiple errors occur following the first error
prior to software clearing the first error register. These bits are sticky through reset.
Software clears these bits by writing a 1 to the bit location.
The errors in this register are reported up into the GLOBAL_NERR registers as either
“fatal” or “non-fatal” errors from the memory controller as noted in the descriptions
below.
Unlike the DRAM_FERR register, multiple errors are accumulated in the DRAM_NERR
register.
Note:
All memory controller errors are “not-fatal”.
Note:
Logging of these errors can be masked only by setting the corresponding bit in Section
16.2.1.38, “Offset 84h: DRAM_EMASK - DRAM Error Mask Register”.
Table 16-91. Offset 82h: DRAM_NERR - DRAM Next Error Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 82h
Offset End: 83h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :08
07
06
05 :04
Bit Acronym
Bit Description
Sticky
Reserved Reserved
MTCA
Memory Test Complete: Not an error condition. This bit
is set by hardware to signal BIOS that hardware testing of
the channel is complete. This bit is sticky through reset.
System software clears this bit by writing a 1 to the
Y
location.
1 = Hardware-based test of DRAM is complete.
(NON-FATAL)
UERRA
Uncorrectable Error on Write: (Uncorrectable) This bit
is set on a detected error regardless of ECC mode, even if
ECC is disabled. However if the error was injected via
ECCDIAG, this bit is not set.
Note that the state of the ECCDIAG.MEMPEN does not
impact the setting of this bit. For more details please see
Section 16.1.1.44, “Offset 84h: ECCDIAG – ECC Detection/
Correction Diagnostic Register”
Y
This bit is sticky through reset. System software clears this
bit by writing a 1 to the location.
0 = No parity error detected on writes to DRAM.
1 = Parity error detected on write to DRAM.
(NON-FATAL)
Reserved Reserved
Bit Reset
Value
00h
0b
0b
00b
Bit Access
RO
RWC
RWC
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
484
August 2009
Order Number: 320066-003US