EP80579 Datasheet, PDF (1046/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.2
IMCH-IICH Messages
NSI messaging protocol is supported. Messages associated with power management
and state transitions are summarized in Table 27-1. The Legacy Protocol messages are
shown only for reference. NSI messages that are not associated with power
management are not shown.
Table 27-1. IMCH-IICH Messages
Legacy
New
Message Message
---
Reset-Warn
---
Stop-
Grant
Go-C0
--
Reset-Warn-
Ack
Stop-Grant
(REQ-C2)
Go-C0
Ack-C0
--
Go-C2
Direction
IICH→IMCH
IMCH→IICH
IMCH→IICH
IICH→IMCH
IMCH→IICH
IICH→IMCH
Description/Comment:
Warning from the IICH to the IMCH that the IICH is about to assert the PLTRST#
signal. The IMCH is expected to acknowledge this with the Reset-Warn-Ack. However,
it the IMCH fails to do this within the timeout period, the IICH will assert the reset.
Acknowledge from the IMCH that it has seen the Reset-Warn message is now ready
for the IICH to cause the reset.
If the processor is in C0 - indication that the processor has issued last Stop-Grant
cycle. The IMCH may receive more than one Stop-Grant cycle from the processor(s).
It is the IMCH’s responsibility to only send the last Stop-Grant.
Indication that system is going back to C0 state.
Acknowledge that IMCH observed the Go-C0 message and is ready to proceed.
This is an indication that the processor has been put into Stop-Grant state.
When coming from C0, this tells the IMCH that it is safe to assert SLP#.
--
Go-C3
Ack-C3
--
Ack-C2
Go-S3
Ack-S3
IMCH→IICH
IICH→IMCH
IMCH→IICH
REQ-C0
(Break-Ind)
IMCH →IICH
IMCH indicates it observed the Go-C2 message and is now ready to proceed.f going
toward C0, the IICH is free to deassert STPCLK#.
Indication that the IICH is getting ready to put the system into S3, S4 or S5 state.
Indication that the IMCH observed the Go-S3 message and is ready to proceed.
This is an indication from the IMCH to the IICH that the IMCH thinks the processor
must be brought to a C0 state. This would be sent for several cases:
1. If the IMCH had received a “Pending Break Event” indication from the processor.
This is needed when PBE# is not muxed with FERR# and is instead muxed with some
pin that goes only to the IMCH.
2. The IMCH has some internal device or link to external device that can cause a
break event that is not associated with an interrupt.
Note: The IMCH is not required to implement this message.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1046
August 2009
Order Number: 320066-003US