EP80579 Datasheet, PDF (1139/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 30-27. APIC_VS - Version Register (Sheet 2 of 2)
Description:
View: IA I
Win:Idx: APIC_WDW:APIC_IDX
Offset Start: 01h (4B)
Offset End: 01h (4B)
Size: 32 bit
Default: 00170020h
Power Well: Core
Bit Range
15
14 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
PRQ
Reserved
VS
Pin Assertion Register Supported: Indicate that the
IOxAPIC does not implement the Pin Assertion Register.
Reserved
Version: Identifies the implementation version as
IOxAPIC. This field reports 20h in all IO-APIC modes
(independent of number of enabled IRQ vectors).
Bit Reset
Value
0h
0h
20h
Bit Access
RO
RO
30.3.4.3
APIC_RTE[0-39] - Redirection Table Entry
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
The APIC responds to an edge triggered interrupt as long as the interrupt is held until
after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine steps ahead and wait for
an acknowledgment from the APIC unit that the interrupt message was sent. Only then
will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge
only results in a new invocation of the handler if its acceptance by the destination APIC
causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the
interrupt was not already pending at the destination.) All bits are undefined except for
bits 47:17 = 0 and bit 16 = 1.
Table 30-28. APIC_RTE[0-39] - Redirection Table Entry (Sheet 1 of 3)
Description:
Offset: vector 0: 10h-11h, vector
Hex)) -(11h + (N*2 in Hex))
1:
12h-13h,
vector
23:
3Eh-3Fh,
vector
39:
5Eh-5Fh;
vector
N:
(10h+
(N*2
in
View: IA I
Win:Idx: APIC_WDW:APIC_IDX
Vector 0
10h at 02h
Offset Start: (4B)
Offset End: 11h at 02h
(4B)
Size: 64 bit^a
Default: XXXX00000001XXXXh
Power Well: Core
Bit Range
63 : 56
55 : 48
47 : 17
Bit Acronym
Bit Description
Sticky
DID
EDID
Reserved
Destination ID: Destination ID of the local APIC.
Extended Destination ID: Extended destination ID of
the local APIC.
Reserved
Bit Reset
Value
X
X
0h
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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