EP80579 Datasheet, PDF (811/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 22-7. Offset 18h: GPO_BLINK - GPIO Blink Enable Register (Sheet 2 of 2)
Description:
View: PCI
Size: 32 bit
BAR: GBA(IO)
Default: 00040000h
Bus:Device:Function: 0:31:0
Offset Start: 18h
Offset End: 1Bh
Power Well: Core^a
Bit Range Bit Acronym
Bit Description
Sticky
25
24 :20
19 : 18
17 :00
The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO functions normally.
1 = If the corresponding GPIO is programmed as an
output, the output signal blinks at a rate of
approximately once per second. The high and low
times have approximately 0.5 seconds each. The
GP_LVL bit is not altered when this bit is set.
The usage model for a blinking output is to control an
GPO_BLINK_25 _{LED. This value does not need to have exactly one}
second granularity, but must be close.
The value of the corresponding GP_LVL bit remains
unchanged during the blink process, and does not effect
the blink in any way.
The GP_LVL bit is not altered when programmed to
blink. It remains at its previous value.
These bits correspond to GPIO in the Resume well and
are reset to their native function by RSMRST# or a write
to the CF9h register or any other PLTRST#.
Reserved Reserved
The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO functions normally.
1 = If the corresponding GPIO is programmed as an
output, the output signal blinks at a rate of
approximately once per second. The high and low
times are approximately 0.5 seconds each. The
GP_LVL bit is not altered when this bit is set. The
GPO_BLINK_19
usage model for a blinking output is to control an
_18
LED. This value does not need to have exactly one
second granularity, but must be close.
The value of the corresponding GP_LVL bit remains
unchanged during the blink process, and does not effect
the blink in any way.
The GP_LVL bit is not altered when programmed to
blink. It remains at its previous value.
These bits correspond to GPIO in the core well and are
reset to their native function by PLTRST#.
Reserved Reserved.
a. Core for 0:7, 16:21, 23; Resume for 8:15, 24:31.
Bit Reset
Value
0b
0h
01b
0h
Bit Access
RW
RO
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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