EP80579 Datasheet, PDF (96/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-3.
Acronym Table
Term
DED
DMA
DW
ECC
EDMA
EMI
EMTS
EOP/EOF
ESD
EXP
FRU
FS
FSB
FWH
GbE
GMII
HBA
HCD
HECBASE
HPET
HSI
I/O
IA
IA-CPU
ICH
IICH
IMCH
INTx
IP
ISA
LEB
LML
LPC
LS
LSb
Description
Double-bit Error Detect
See Direct Memory Access in Table 1-4.
Double Word. A legacy reference to 32 bits of data on a naturally aligned four-byte
boundary (i.e. the least significant two bits of the byte address are b00). This is a legacy
term used by PCI and must not be used other than in that context.
Error Checking and Correction
Enhanced DMA
Electro Magnetic Interference
Electrical Mechanical Thermal Specification used for processor specifications.
End Of Packet / End Of Frame
Electrostatic Discharge
A generic designation for the I/O interconnect technology also known as PCI Express*.
Field Replaceable Unit
Full-speed. Refers to USB.
Front Side Bus (a common external interface for IA processors)
Firmware Hub. A non-volatile memory device used to store the system BIOS/pre-boot
firmware.
Gigabit Ethernet controller
Gigabit MII
Host Bus Adapter - necessary when connecting a peripheral to a computer that doesn’t
have native support for that peripheral’s interface.
Host Controller Device - USB interface for programmers
PCI Express* Enhanced Configuration Base Register
High Precision Event Time (HPET) - The IA-PC HPET Architecture defines a set of timers
that can be used by the operating system. The timers are defined such that the OS may
be able to assign specific timers to be used directly by specific applications. Each timer
can be configured to generate a separate interrupt.
High Speed Interface. Refers to USB.
1. Input/Output. 2. When used as a qualifier to a transaction type, specifies that
transaction targets Intel Architecture™ specific I/O space (e.g., I/O read).
Intel Architecture instruction set commonly known as “x86”
IA-CPU, IA Complex and IA Processor are the same terminology
I/O Controller Hub, ICH and IICH are interchangeable for entire document
Integrated I/O Controller Hub, ICH and IICH are interchangeable for entire document
Integrated Memory Controller Hub, MCH and IMCH are interchangeable for the entire
document
Legacy PCI interrupt architecture that encodes interrupts on one of four side-band signals
(INTA, INTB, INTC, and INTD).
Internet Protocol
See Industry Standard Architecture in Table 1-4
Local Expansion Bus, or LE Bus
Latency Measurement Logic
Low Pin Count
Low-speed. Refers to USB.
Least Significant Bit
Intel^® EP80579 Integrated Processor Product Line Datasheet
96
August 2009
Order Number: 320066-003US