EP80579 Datasheet, PDF (74/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
29-4
29-5
29-6
29-7
30-1
30-2
30-3
30-4
30-5
30-6
30-7
30-8
30-9
30-10
30-11
30-12
30-13
30-14
30-15
30-16
30-17
30-18
30-19
30-20
30-21
30-22
30-23
30-24
30-25
30-26
30-27
30-28
30-29
30-30
31-1
31-2
31-3
31-4
31-5
31-6
31-7
31-8
32-1
32-2
32-3
32-4
32-5
32-6
32-7
32-8
33-1
33-2
33-3
33-4
33-5
Offset 0Ah: RTC_REGA - Register A (General Configuration) ............................... 1107
Offset 0Bh: RTC_REGB - Register B (General Configuration) ............................... 1109
Offset 0Ch: RTC_REGC - Register C (Flag Register) ........................................... 1110
Offset 0Dh: RTC_REGD - Register D (Flag Register) .......................................... 1111
Interrupt Options - 8259 Mode ......................................................................... 1115
Interrupt Options - APIC Mode.......................................................................... 1116
Signals Associated with Interrupt Logic .............................................................. 1117
8259 Core Connection .................................................................................... 1117
Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space ........... 1118
ICW1[0-1] - Initialization Command Word 1 Register .......................................... 1119
ICW2[0-1] - Initialization Command Word 2 Register ......................................... 1120
MICW3 - Master Initialization Command Word 3 Register ................................... 1121
SICW3 - Slave Initialization Command Word 3 Register ..................................... 1121
ICW4[0-1] - Initialization Command Word 4 Register .......................................... 1122
OCW1[0-1]- Operational Control Word 1 (Interrupt Mask) Register ....................... 1122
OCW2[0-1] - Operational Control Word 2 Register .............................................. 1123
OCW3[0-1] - Operational Control Word 3 Register ............................................. 1124
ELCR1 - Master Edge/Level Control Register ..................................................... 1125
ELCR2 - Slave Edge/Level Control Register ....................................................... 1126
Interrupt Handling ......................................................................................... 1127
Content of Interrupt Vector Byte....................................................................... 1127
Interrupt Delivery Address Format ................................................................... 1134
Interrupt Delivery Data Format ........................................................................ 1134
Summary of APIC Registers Mapped in Memory Space“........................................ 1135
APIC_IDX - Index Register .............................................................................. 1135
APIC_DAT – Data Register ............................................................................. 1136
APIC_EOI - EOI Register ................................................................................ 1136
APIC Index Register Space............................................................................... 1137
Summary of APIC Indexed Registers ................................................................. 1137
APIC_ID – Identification Register ..................................................................... 1138
APIC_VS - Version Register ............................................................................ 1138
APIC_RTE[0-39] - Redirection Table Entry ........................................................ 1139
Stop Frame Definition ..................................................................................... 1143
Data Frame Format......................................................................................... 1144
SPKR Signal ................................................................................................... 1145
Summary of 8254 Timer Registers Mapped in I/O Space ...................................... 1145
Offset 43h: TCW - Timer Control Word Register .................................................. 1146
Offset 40h: TSB[0-2] - Interval Timer Status Byte Format Register ..................... 1147
Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register ................... 1148
Counter Operating Modes ............................................................................... 1149
Counter Latch Command ................................................................................ 1150
Read Back Command ..................................................................................... 1151
Summary of HPET Registers Mapped in Memory Space ........................................ 1154
Offset 000h: GCAP_ID - General Capabilities and ID Register ............................. 1155
Offset 010h: GEN_CONF - General Configuration Register ................................... 1156
Offset 020h: GINTR_STA - General Interrupt Status Register ............................... 1157
Offset 0F0h: MAIN_CNT - Main Counter Value Register ....................................... 1158
Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register .......... 1159
Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register ........................... 1163
Legacy Replacement Routing............................................................................ 1164
Address Map ................................................................................................. 1170
Supported LPC Cycle Types ............................................................................. 1170
I/O Sync Bits Description ................................................................................ 1171
UART Clock Divider Support ............................................................................ 1172
Baud Rate Example ........................................................................................ 1172
Intel^® EP80579 Integrated Processor Product Line Datasheet
74
August 2009
Order Number: 320066-003US