EP80579 Datasheet, PDF (1131/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.7
30.2.7.1
30.2.7.2
30.2.8
30.2.8.1
30.2.8.2
30.2.9
End of Interrupt (EOI) operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to 1.
Normal EOI
In Normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears
the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of
operation of the PIC within the IICH, as the interrupt being serviced currently is the
interrupt entered with the interrupt acknowledge. When the PIC is operated in modes
which preserve the fully nested structure, software can determine which ISR bit to
clear by issuing a Specific EOI.
An ISR bit that is masked will not be cleared by a Non-Specific EOI if the PIC is in the
Special Mask Mode. An EOI command must be issued for both the master and slave
controller.
Automatic EOI Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode must be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller.
Masking Interrupts
Masking on an Individual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller masks all requests for service
from the slave controller.
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The Special Mask Mode enables all interrupts not masked by a bit set in the Mask
Register. Normally, when an interrupt service routine acknowledges an interrupt
without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower
priority requests. In the Special Mask Mode, any interrupts may be selectively enabled
by loading the Mask Register with the appropriate pattern. The special Mask Mode is set
by OCW3.SSMM and OCW3.SMM set, and cleared when OCW3.SSMM and OCW3.SMM
are cleared.
Steering of PCI Interrupts
The IICH can be programmed to allow PIRQA#-PIRQH# to be internally routed to
interrupts 3-7, 9-12, 14 or 15, through the PARC, PBRC, PCRC, PDRC, PERC, PFRC,
PGRC, and PHRC registers in Section 19.2.3.1, “Offset 60h: PARC: PIRQA Routing
Control Register” on page 741. The assignment is programmable through the PIRQx
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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