EP80579 Datasheet, PDF (1054/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.2.1
Offset B2h: APM_CNT - Advanced Power Management Control Port
Register
Used to pass an APM command between the OS and the SMI handler. Writes to this port
not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
Table 27-8. Offset B2h: APM_CNT - Advanced Power Management Control Port Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: B2h
Offset End: B2h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
APM_CNT
Used to pass an APM command between the OS and the
SMI handler. Writes to this port not only store data in
the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
Bit Reset
Value
00h
Bit Access
RW
27.3.2.2
Offset B3h: APM_STS - Advanced Power Management Status Port
Register
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not effected by any other register or function (other than a PCI reset).
Table 27-9. Offset B3h: APM_STS - Advanced Power Management Status Port Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: B3h
Offset End: B3h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
APM_STS
Used to pass data between the OS and the SMI handler.
Basically, this is a scratchpad register and is not affected
by any other register or function (other than a platform
reset).
Bit Reset
Value
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1054
August 2009
Order Number: 320066-003US