EP80579 Datasheet, PDF (1289/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.9.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control Register
Table 35-88. Offset F2h: MCTL: Message Signalled Interrupt Control Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: F2h
Offset End: F3h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: F2h
Offset End: F3h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 09
08
07
06 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
MC
C64
MME
MMC
MSIE
Reserved
Per-Vector Masking Capable: Hardwired to 0 to indicate
the device is not capable of per-vector masking.
64 bit Address Capable: Hardwired to 0 to indicate the
device does not generate 64b message addresses.
Multiple Message Enable: System software writes to this
field to indicate the number of allocated messages (less
than or equal to the number of requested messages in
MMC). A value of 0 corresponds to one message.
Multiple Message Capable: System software reads this
field to determine the number of requested messages.
Hardwired to 0 to request one message.
MSI Enable: System software sets this bit to enable MSI
signaling. A device driver is prohibited from writing this bit
to mask a device’s service request.
If 1, the device can use an MSI to request service.
If 0, the device cannot use an MSI to request service.
Bit Reset
Value
0h
0h
0h
000h
000h
0h
Bit Access
RO
RO
RO
RW
RO
RW
35.9.1.31 Offset F4h: MADR – Message Signalled Interrupt Address Register
Table 35-89. Offset F4h: MADR: Message Signalled Interrupt Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: F4h
Offset End: F7h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: F4h
Offset End: F7h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
ADDR
Message Address: Written by the system to indicate the
lower 32-bits of the address to use for the MSI memory
write transaction. The lower two bits will always be written
as 0.
Bit Reset
Value
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1289