EP80579 Datasheet, PDF (296/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 11-1. Memory Address Tables for 64 Bit, Burst Size 4 and x8 DDR2 Devices
T o ta l
Cap
(M B )
S in g le
Rank
Dev
Device ice Bus
densty w idt W id R /C /B
(M b) h th addr lines
BA2 BA1 BA0 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
256
Row 0
256 8 64 13x10x2 Col
7
6
0
0
0 26 25 24 23 22 21 20 19 18 17 16 15 14
0 0 0 AP 27 13 12 11 10 9 8 5 0
0
512
Row 0
7
6
0 28 26 25 24 23 22 21 20 19 18 17 16 15 14
512 8 64 14x10x2 Col
0 0 0 0 AP 27 13 12 11 10 9 8 5 0
0
1024
1024
8
Row
64 14x10x3 Col
8
7
6
0 28 26 25 24 23 22 21 20 19 18 17 16 15 14
0 0 0 0 AP 27 13 12 11 10 9 29 5 0
0
2048
2048
8
Row
64 15x10x3 Col
8
7
6 30 28 26 25 24 23 22 21 20 19 18 17 16 15 14
0 0 0 0 AP 27 13 12 11 10 9 29 5 0
0
Figure 11-2. Memory Address Tables for 32 Bit, Burst Size 8 and x8 DDR2 Devices
D evice
d en sty
(M b)
Dev
ice B us
w idt W id
h th
R /C /B
add r lin es
BA2 BA1 BA0 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
Row 0 7 6 0 0 26 25 24 23 22 21 20 19 18 17 16 15 14
256 8 32 13x10x2 Col
0 0 0 0 AP 13 5 12 11 10 9 8 0 0
0
Row 0 7 6 0 27 26 25 24 23 22 21 20 19 18 17 16 15 14
512 8 32 14x10x2 Col
0 0 0 0 AP 13 5 12 11 10 9 8 0 0
0
Row 8 7 6 0 27 26 25 24 23 22 21 20 19 18 17 16 15 14
1024 8 32 14x10x3 Col
0 0 0 0 AP 13 5 12 11 10 9 28 0 0
0
Row 8 7 6 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14
2048 8 32 15x10x3 Col
0 0 0 0 AP 13 5 12 11 10 9 28 0 0
0
11.3.4
DRAM Timings
The EP80579 is highly configurable in its DRAM timing configuration, but only a limited
subset of the setting combinations possible are verified by Intel. The approved and
expected settings for the various flavors of supported memory are listed in
Table 11-12. For more information on the DRT register see “Offset 78h: DRT0 - DRAM
Timing Register 0” and “Offset 64h: DRT1 – DRAM Timing Register 1”.
Table 11-12. Supported DRAM Timings
Memory Speed
CL
(CAS latency)
tRCD
(RAS-CAS delay)
DDR2-400^a
DDR2-400^b
3
3
4
4
DDR2-533
4
4
DDR2-667
5
5
DDR2-800
5
5
6
6
a: 3-3-3 is not supported for systems which require ODT
b: May be accomplished by programming 3-3-3 parts to 4-4-4
tRP
(RAS Precharge)
3
4
4
5
5
6
Intel^® EP80579 Integrated Processor Product Line Datasheet
296
August 2009
Order Number: 320066-003US