EP80579 Datasheet, PDF (8/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
10.5.1.2 SMM Space Definition ...................................................................... 282
10.6 Memory Reclaim Background............................................................................. 283
10.6.1 Memory Remapping Algorithm.................................................................. 283
10.7 IICH Register and Memory Mappings .................................................................. 284
10.7.1 I/O Map ................................................................................................ 284
10.7.1.1 Fixed I/O Address Ranges ................................................................ 284
10.7.1.2 Variable I/O Decode Ranges ............................................................. 286
10.7.2 Memory Map .......................................................................................... 287
10.7.3 Boot-Block Update Scheme ...................................................................... 288
11.0 System Memory Controller ..................................................................................... 289
11.1 Overview ........................................................................................................ 289
11.2 Memory Controller Feature List .......................................................................... 289
11.3 Configurations ................................................................................................. 291
11.3.1 Rules for Populating DIMM Slots ............................................................... 293
11.3.2 DRAM Addressing ................................................................................... 294
11.3.3 Memory Address Translation Tables .......................................................... 295
11.3.3.1 DDR2 Address Translation Tables ...................................................... 295
11.3.4 DRAM Timings........................................................................................ 296
11.3.4.1 2T Timing Mode .............................................................................. 297
11.3.5 DQ/DQS Mapping ................................................................................... 298
11.3.6 32-Bit Mode ........................................................................................... 298
11.4 DDR2 Features ................................................................................................ 298
11.4.1 Interface Signalling Voltage ..................................................................... 298
11.4.2 On-DIMM Die Termination (ODT) .............................................................. 299
11.4.2.1 ODT Control of Reads ...................................................................... 300
11.4.2.2 ODT Control of Writes ...................................................................... 300
11.4.3 On-Die Termination (ODTZ) on the EP80579 ............................................. 301
11.4.4 Refresh ................................................................................................. 302
11.4.5 Self-Refresh........................................................................................... 302
11.4.6 RCOMP.................................................................................................. 303
11.4.7 DDR2 MR and EMR settings...................................................................... 303
11.4.8 Scrubbing Support .................................................................................. 304
11.4.8.1 Demand Scrubbing .......................................................................... 304
11.4.8.2 Background Scrubbing ..................................................................... 304
11.5 Error Handling................................................................................................. 304
12.0 Enhanced Direct Memory Access Controller (EDMA) ............................................... 307
12.1 Overview ........................................................................................................ 307
12.1.1 Features................................................................................................ 308
12.1.2 Logical Block Diagram ............................................................................. 309
12.2 Channel Programming Interface......................................................................... 310
12.3 Chaining Operation .......................................................................................... 311
12.3.1 Chain Descriptor Definition ...................................................................... 311
12.3.2 DMA Chain Descriptor in Memory .............................................................. 312
12.3.3 Chain Descriptor Usage ........................................................................... 312
12.3.4 Scatter/Gather Transfer........................................................................... 314
12.3.5 Appending to a Descriptor Chain ............................................................... 314
12.3.6 Splicing a Descriptor Chain into a Linked List.............................................. 315
12.4 Transfer Types ................................................................................................ 316
12.4.1 Local Memory to Local Memory................................................................. 316
12.4.2 Local Memory to I/O Subsystem Memory ................................................... 316
12.4.3 I/O Memory to Local Memory ................................................................... 317
12.4.4 I/O Memory to I/O Memory...................................................................... 317
12.5 Addressing...................................................................................................... 317
12.5.1 Address Coherence ................................................................................. 317
Intel^® EP80579 Integrated Processor Product Line Datasheet
8
August 2009
Order Number: 320066-003US