EP80579 Datasheet, PDF (930/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-45. Summary of Enables for the Host Notify Command
HOST_NOTIFY_INTREN
(Slave Control I/O Register,
Offset 11h, bit 0)
0
X
1
1
SMB_SMI_EN (Host
Configuration Register,
D31, F3, Off40h, Bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O Register,
Offset 11h, bit 1)
Result
X
0
None
X
1
Wake generated
0
X
Interrupt generated
1
X
Slave SMI# generated
(SMBUS_SMI_STS)
24.8
CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the CMI automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and checks the
CRC for read cycles. It does not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior results.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch is set.
24.8.1
Slave Interface I/O Space
The following registers are used by the SMBus Slave logic. Refer to Section 24.3 for the
complete list of SMB I/O Registers.
Table 24-46. Bus 0, Device 31, Function 3, Slave PCI Registers Mapped Through SM_Base
(IO)
Offset Start Offset End
Register ID - Description
09h
09h
“Offset 09h: RSA: Receive Slave Address Register” on page 931
0Ah
0Bh
“Offset 0Ah: SD: Slave Data Register” on page 931
10h
10h
“Offset 10h: SSTS: Slave Status Register” on page 932
11h
11h
“Offset 11h: SCMD: Slave Command Register” on page 932
14h
14h
“Offset 14h: NDA: Notify Device Address Register” on page 933
16h
16h
“Offset 16h: NDLB: Notify Data Low Byte Register” on page 934
17h
17h
“Offset 17h: NDHB: Notify Data High Byte Register” on page 934
Default
Value
44h
0000h
00h
00h
00h
00h
00h
Intel^® EP80579 Integrated Processor Product Line Datasheet
930
August 2009
Order Number: 320066-003US