EP80579 Datasheet, PDF (519/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.3.1.24 Offset B4h: MSIAR - MSI Address Register
The MSI Address Register (MSIAR) contains all the address related information to route
MSI interrupts.
Table 16-136.Offset B4h: MSIAR - MSI Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: B4h
Offset End: B7h
Size: 32 bit
Default: FEE00000h
Power Well: Core
Bit Range
31 : 20
19 : 12
11 : 04
03
02
01 : 00
Bit Acronym
Bit Description
Sticky
MSIADD
MSIDID
MSIEDID
RDRCTID
DSTMD
Reserved
Address: Most significant 12 bits of the 32-bit address.
Destination ID: Should reflect the 63:56 bits of IOxAPIC
redirection table entry.
Extended Destination ID: Should reflect the 55:48 bits
of IOxAPIC redirection table entry.
Redirection Hint: Allows the interrupt message to be
redirected.
0 = Direct. Message is delivered to the agent listed in bits
19:12
1 = Redirect. Message is delivered to an agent with a
lower interrupt priority. This can be derived from bits
10:08 of the Data field
Destination Mode: Used only if the Redirection Hint bit is
set to 1.
0 = Physical
1 = Logical
Reserved.
Bit Reset
Value
FEEh
00h
00h
0b
0b
00b
Bit Access
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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