EP80579 Datasheet, PDF (1291/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.10
35.10.1
SSP Controller Configuration Space: Bus M, Device 6,
Function 0
The SSP controller is Device 6 of Bus M, and is accessed using type 1 configuration
cycles
Register Details
Table 35-91. Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration
Registers
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
09h
0Eh
10h
2Ch
2Eh
34h
3Ch
3Dh
DCh
DDh
DEh
E0h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
F1h
F2h
F4h
F8h
01h
03h
05h
07h
08h
0Bh
0Eh
13h
2Dh
2Fh
34h
3Ch
3Dh
DCh
DDh
DFh
E1h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
F1h
F3h
F7h
F9h
“Offset 00h: VID: Vendor Identification Register” on page 1292
8086h
“Offset 02h: DID: Device Identification Register” on page 1292
503Bh
“Offset 04h: PCICMD: Device Command Register” on page 1292
0000h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1293
0010h
“Offset 08h: RID: Revision ID Register” on page 1294
Variable
“Offset 09h: CC: Class Code Register” on page 1295
078000h
“Offset 0Eh: HDR: Header Type Register” on page 1295
00h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1295
00000000h
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1296
0000h
“Offset 2Eh: SID: Subsystem ID Register” on page 1296
0000h
“Offset 34h: CP: Capabilities Pointer Register” on page 1297
DCh
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1297
00h
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1297
01h
“Offset DCh: PCID: Power Management Capability ID Register” on page 1298
01h
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1298
E4h
“Offset DEh: PMCAP: Power Management Capability Register” on page 1298
0023h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1299
0000h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1300
09h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1300 F0h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1300
09h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1301
01h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1301
00h
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1302
00h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1302
05h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
page 1302
00h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1303 0000h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1303 00000000h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1304 0000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1291