EP80579 Datasheet, PDF (935/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.9
Note:
Slave Interface Behavioral Description
The SMBus slave logic does not generate or handle receiving the PEC byte. There is no
ASF support.
The slave interface allows the CMI to decode cycles on SMLink in TCO compatible
mode, and allows an external microcontroller to perform specific actions. Key features
and capabilities:
• Supports decode of three types of messages: byte write, byte read, and host notify
• Register for the receive slave address. This is the address that the CMI decodes. A
default value is provided so that the slave interface can be used without the
processor having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller
• Registers that the external microcontroller can read to get the state
• Status bits to indicate that the SMLink/SMBus slave logic caused an interrupt or
SMI#
— Bit 0 of the slave status register for the host notify command
— Bit 16 of the SMI Status Register for all others
The external microcontroller should not attempt to access the SMBus slave logic until
one second after both: RTEST# is high and RSMRST# is high.
If a master leaves the clock and data bits of the SMLink or SMBus interface at '1' for 50
µs or more in the middle of a cycle, the slave logic's behavior is undefined. This is
interpreted as an unexpected idle and should be avoided when performing
management activities to the slave logic.
24.9.1
Format of Slave Write Cycle
The external master performs byte write commands to the SMBus Slave Interface. The
Command field (bits 11 – 18) indicate which register is being accessed. The Data field
(bits 20 – 27) indicate the value that should be written to that register.
The write cycle format is shown below in Table 24-54. Table 24-55 has the values
associated with the registers.
Table 24-54. Slave Write Cycle Format
Bit
1
2–8
9
10
Description
Start Condition
Slave Address - 7 bits
Write
ACK
Driven By
External Microcontroller
External Microcontroller
External Microcontroller
CMI
11 – 18 Command
External Microcontroller
19 ACK
20 – 27 Register Data
28 ACK
29 Stop
CMI
External Microcontroller
CMI
External Microcontroller
Comment
Must match value in Receive Slave Address register
Hardwired to 0
This field indicates which register will be accessed.
See Table 24-55 for the register definitions
See Table 24-55 for the register definitions
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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