EP80579 Datasheet, PDF (1207/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The desired configuration registers are accessed in two steps:
1. Write the index of the Logical Device Number Configuration Register (i.e., 07) to
the INDEX PORT and then write the number of the desired logical device to the
DATA PORT.
2. Write the address of the desired configuration register within the logical device to
the INDEX PORT and then write or read the configuration register through the DATA
PORT.
Note:
If accessing the Global Configuration Registers, step (1) is not required. The chip
returns to the RUN State.
Note:
Only two states are defined (Run and Configuration). In the Run State the chip is
always ready to enter the Configuration State.
33.8.3
Warning:
SIW Configuration Register Summary
The default values are defined with an h for hex, a bi for binary, or 00 for zero. If there
is not a letter following the default value, assume it is a binary number.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Note:
Reserved bits are Read Only.
Table 33-38. Configuration Register Summary (Sheet 1 of 2)
Global Configuration Registers
Index
07h
20h
21h
28h
29h
2Eh
30h
60h
61h
70h
74h
75h
F0h
30h
60h
61h
70h
Type
RW
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
Configuration Register
00h
Logical Device Number
00h
Device ID
01h
Device Rev
01h
SIW I/F (wait states)
02h
SIRQ Configuration
00h
Test Mode Configuration Register
Logical Device 4 Registers (Serial Port 1)
00h
Enable
00h
Base I/O Address MSB
00h
Base I/O Address LSB
00h
Primary Interrupt Select
04h
RSVD
04h
RSVD
00h
RSVD
Logical Device 5 Registers (Serial Port 2)
00h
Enable
00h
Base I/O Address MSB
00h
Base I/O Address LSB
00h
Primary Interrupt Select
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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