EP80579 Datasheet, PDF (927/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
There is no STOP condition before the repeated START condition, and that a NACK
signifies the end of the read transfer.
Note:
E32B in the Auxiliary Control register must be set when using this protocol.
Table 24-42. Block Write-Block Read Process Call Protocol with/without PEC
Bit
Description
1
Start
2 – 8 Slave Address - 7 bits
9
Write
10 Acknowledge from Slave
11 – 18 Command code - 8 bits
19 Acknowledge from slave
20 – 27 Data Byte Count (M) - 8 bits
28 Acknowledge from Slave
29 – 36 Data Byte (1) - 8 bits
37 Acknowledge from slave
38 – 45 Data Byte (2) - 8 bits
46 Acknowledge from slave
…
…
Data Byte (M) - 8 bits
Acknowledge from slave
Repeated Start
Slave Address - 7 bits
Read
Acknowledge from slave
Data Byte Count (N) from slave – 8 bits
Acknowledge from master
Data Byte (1) from slave – 8 bits
Acknowledge from master
Data Byte (2) from slave – 8 bits
Acknowledge from master
…
…
Data Byte Count (N) from slave – 8 bits
Acknowledge from master (Skip if no PEC)
PEC from slave (Skip if no PEC)
NOT acknowledge
Stop
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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