EP80579 Datasheet, PDF (552/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.38 Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register
This register points to the next capability structure.
Table 16-177.Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 59h
Offset End: 59h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 59h
Offset End: 59h
Size: 8 bit
Default: 64h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
MSI_NCP
Next Capability Pointer: This field points to the next
Capability ID in this device, which is the Hot Plug
Controller.
Sticky
Bit Reset
Value
Bit Access
64h
RO
16.4.1.39 Offset 5Ah: MSICAPA - MSI Capabilities Register
The PCI Express* controller generates upstream interrupt message using MSI to the
processor bypassing IOxAPIC. The MSI is generated by a Memory Write to address
0FEEx_xxxxh. Three 32-bit registers are required in the PCI Express* controller to
support this mechanism. The default values of these registers are compatible to the
default value of IOxAPIC. The software can reprogram these registers to required
value. The three registers are MSI Control Register (MSICR), MSI Address Register
(MSIAR) and MSI Data Register (MSIDR). Depending on system requirement each PCI
Express* channel can have a MSI block (provides better flexibility) or the PCI Express*
controller as a whole has one MSI block and all channels raise hardware interrupts to
this block.
The MSI Control Register (MSICR) contains all the information related to the capability
of PCI Express* MSI interrupts. The MSICR register has been broken down into its
components, MSICAPID, MSINPTR, and MSICAPA for purposes of separate register
definitions.
Intel^® EP80579 Integrated Processor Product Line Datasheet
552
August 2009
Order Number: 320066-003US