EP80579 Datasheet, PDF (1009/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.3.2.2
Offset 24h: USB2STS - USB 2.0 Status Register
This register indicates pending interrupts and various states of the Host Controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to 0 in this register by writing a 1 to it. See the Interrupts
description in section 4 of the EHCI Specification for additional information concerning
USB 2.0 interrupt conditions.
Table 26-41. Offset 24h: USB2STS - USB 2.0 Status Register (Sheet 1 of 3)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 24h
Offset End: 27h
Size: 32 bit
Default: 00001000h
Power Well: Core
Bit Range
31 :16
15
14
13
12
11 :06
05
Bit Acronym
Bit Description
Sticky
Reserved
ASY_SSTAT
PER_SSTAT
RECL
HCH
Reserved
INT_ASYA
Reserved.
Asynchronous Schedule Status: This bit reports the
current real status of the Asynchronous Schedule.
0 = The status of the Asynchronous Schedule is disabled.
1 = The status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable
or enable the Asynchronous Schedule when software
transitions the Asynchronous Schedule Enable bit in the
USBCMD register. When this bit and the Asynchronous
Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (1) or disabled (0).
Periodic Schedule Status: This bit reports the current
real status of the Periodic Schedule.
0 = The status of the Periodic Schedule is disabled.
1 = The status of the Periodic Schedule is enabled.
The Host Controller is not required to immediately disable
or enable the Periodic Schedule when software transitions
the Periodic Schedule Enable bit in the USBCMD register.
When this bit and the Periodic Schedule Enable bit are the
same value, the Periodic Schedule is either enabled (1) or
disabled (0).
Reclamation: This is a read-only status bit, which is used
to detect an empty asynchronous schedule. The
operational model and valid transitions for this bit are
described in Section 4 of the EHCI Specification.
HCHalted:
0 = This bit is a zero whenever the Run/Stop bit is a one.
1 = The Host Controller sets this bit to 1 after it has
stopped executing as a result of the Run/Stop bit
being set to 0, either by software or by the Host
Controller hardware (e.g., internal error).
Reserved.
Interrupt on Async Advance: System software can
force the host controller to issue an interrupt the next
time the host controller advances the asynchronous
schedule by writing a one to the Interrupt on Async
Advance Doorbell bit in the USBCMD register. This status
bit indicates the assertion of that interrupt source.
Bit Reset
Value
0h
0h
0h
0h
1h
0h
0h
Bit Access
RO
RO
RO
RO
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1009