EP80579 Datasheet, PDF (1322/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-153.Offset 06h: PCISTS: PCI Device Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0010h
Power Well: Core
Bit Range
10 : 09
08
07
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
DST
MDPE
FB2B
Reserved
MC66
CL
IS
Reserved
DEVSEL Timing: The device does not implement this
functionality. These bits are hardwired to 0.
Master Data Parity Error Detected: The device does not
implement this functionality. The bit is hardwired to 0. The
EP80579 uses signals for errors.
Fast Back-to-Back Capable: The device does not
implement this functionality. The bit is hardwired to 0.
Reserved
66 MHz Capable: The device does not implement this
functionality. The bit is hardwired to 0.
Capabilities List: This bit is hardwired to 1 to indicate
that the device has a capabilities list.
Interrupt Status:
Reserved
Bit Reset
Value
00b
0h
0h
0h
0h
1
0h
0h
Bit Access
RO
RO
RO
RV
RO
RO
RO
RV
35.12.1.5 Offset 08h: RID – Revision ID Register
The value of this register comes from the ICH Compatibility Rev ID registers.
Table 35-154.Offset 08h: RID: Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Revision Identification Number: This value indicates
the revision identification number for the AIOC Device.
RID
The 4 most significant bits are always 0. The 4 least
significant bits follow the ICH revision ID scheme as
defined in Section 19.2.1.4, “Offset 08h: RID - Revision ID
Register” on page 736.
Bit Reset
Value
Variable
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1322
August 2009
Order Number: 320066-003US