EP80579 Datasheet, PDF (1678/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Once the cycle type has been determined, the mode of operation must be set. There
are two configurable modes of operation for each chip select, multiplexed and non-
multiplexed. Bit 4 of the Timing and Control (EXP_TIMING_CS) Registers is used to
select this mode. If bit 4 of the Timing and Control (EXP_TIMING_CS) Register is set to
logic 1, the access mode for that Chip Select is multiplexed. Likewise, if bit 4 of the
Timing and Control (EXP_TIMING_CS) Register is cleared to logic 0, the access mode
for that Chip Select is non-multiplexed. For Synchronous Intel, Micron ZBT memories
bit 4 must be programmed to logic 0. Multiplexed and non-multiplexed can imply
different operations depending upon the Cycle Type that is selected.
The size of the data bus for each device connected to the Expansion bus must be
configured. The data bus size is selected on a per-chip-select basis, allowing the most
flexibility when connecting devices to the Expansion bus. There are two valid selections
that can be configured for each data bus size, 8-bit or 16-bit. Bit 0 f each Timing and
Control (EXP_TIMING_CS) Register is used to select the data bus size on a per-chip-
select basis.
Each chip select can be independently enabled or disabled by setting a value in bit 31 of
each Timing and Control (EXP_TIMING_CS) Register. Clearing bit 31 of the Timing and
Control (EXP_TIMING_CS) Register to logic 0 disables the corresponding chip select.
Setting bit 31 of the Timing and Control (EXP_TIMING_CS) Register to logic 1 enables
the corresponding chip select. Accesses to chip selects that are disabled result in an
error response.
Split transfers are supported for all read transfer types and controlled by setting bit 3
(SPLT_EN) of the Timing and Control (EXP_TIMING_CS) Register. Setting bit 3 of each
Timing and Control (EXP_TIMING_CS) Register to logic 1 enables split transfers for
accesses to the corresponding chip select. Clearing bit 3 of each Timing and Control
(EXP_TIMING_CS) Register to logic 0 disables split transfers for accesses to the
corresponding chip select. Enabling split transactions allows for more efficient
utilization of the internal bus, especially for slow external expansion bus devices. For
higher performance devices with low read latencies, disabling split transactions may
provide better performance.
Each chip select region has the ability to be write-protected by setting bit 1 of each
Timing and Control (EXP_TIMING_CS) Register. When bit 1 of Timing and Control
(EXP_TIMING_CS) Register is cleared to logic 0, writes to a specified chip select region
results in an error response. When bit 1 of Timing and Control (EXP_TIMING_CS)
Register is set to logic 1, writes are allowed to a specified chip select region. Chip select
0 will be write-protected after reset.
For chip selects 4 through 7 configured in HPI mode of operation, there is an associated
ready bit (EX_RDY [3:0]). The ready bit is only used when the mode of operation is set
to Texas Instruments HPI mode. The ready bits are used to hold off the host processor
when the given DSP is not ready to complete the transfer. However, the polarity of this
ready bit can vary based upon the DSP that is selected. Bit 5 of each Timing and
Control (EXP_TIMING_CS) Register allows the polarity used by each ready bit to be
independently set. When bit 5 of the Timing and Control (EXP_TIMING_CS) Register is
cleared to logic 0, the ready bit is cleared to respond to an active low signal (logic 0).
When bit 5 of the Timing and Control (EXP_TIMING_CS) Register is set to logic 1, the
ready bit is set to respond to an active high signal (logic 1).
One final set of parameters that may be set prior to using Expansion Bus Interface Chip
Select 1 through Chip Select 8. After boot up, these parameters may be adjusted for
Chip Select 0 as well. These five parameters are the timing extension parameters for
each phase of an Expansion Bus access.
There are five phases to every Expansion Bus access:
• T1 – Address Timing
• T2 – Setup/Chip Select Timing
Intel^® EP80579 Integrated Processor Product Line Datasheet
1678
August 2009
Order Number: 320066-003US