EP80579 Datasheet, PDF (507/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-123.Offset 2Eh: SID - Subsystem Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SUBID
Subsystem ID: This field must be programmed during
BIOS initialization. When any byte or combination of bytes
of this register is written, the register value locks and
cannot be further updated.
Bit Reset
Value
0000h
Bit Access
RWO
16.3.1.12 Offset 34h: CAPPTR - Capabilities Pointer Register
The CAPPTR provides the offset that is the pointer to the location where the first set of
capabilities registers is located.
Table 16-124.Offset 34h: CAPPTR - Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: B0h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
CAP_PTR
Capabilities Pointer: Pointer to first capabilities
structure.
Sticky
Bit Reset
Value
Bit Access
B0h
RO
16.3.1.13 Offset 3Ch: INTRLINE - Interrupt Line Register
Table 16-125.Offset 3Ch: INTRLINE - Interrupt Line Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
INTRLINE
Interrupt Connection: BIOS writes the interrupt routing
information to this register to indicate which input of the
interrupt controller is connected with this device.
Bit Reset
Value
00h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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