EP80579 Datasheet, PDF (539/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom four bits of this register are
read-only and return zeroes when read. This register must be initialized by
configuration software. For the purpose of address decode address bits A[19:00] are
assumed to be FFFFFh. Thus, the top of the defined memory address range is at the top
of a 1 Mbyte aligned memory block.
Memory range covered by MBASE and MLIMIT registers, are used to map non-
prefetchable PCI Express* address ranges (typically where control/status memory-
mapped I/O data structures of the graphics controller reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved PCI
Express* memory access performance.
Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges;
for example, to prevent overlap with each other and/or with the ranges covered with
the main memory. There is no provision in the CMI hardware to enforce prevention of
overlap and operations of the system in the case of overlap are not guaranteed.
Table 16-157.Offset 22h: MLIMIT - Memory Limit Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 22h
Offset End: 23h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 22h
Offset End: 23h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
MILIMIT
Reserved
Memory Address Limit: Corresponds to A[31:20] of the
memory address that corresponds to the upper limit of the
range of memory accesses that are passed by the device
bridge to PCI Express*.
Reserved
Bit Reset
Value
000h
0h
Bit Access
RW
16.4.1.19 Offset 24h: PMBASE - Prefetchable Memory Base Address Register
This PMBASE and PMLIMIT register controls the processor to PCI Express* prefetchable
memory accesses. The upper 12 bits of the register are read/write and correspond to
the upper 12 address bits A[31:20] of the 32-bit address. For the purpose of address
decode, bits A[19:00] of the Prefetchable Memory Base Address are assumed to be 0.
similarly, the bridge assumes that the lower 20 bits of the Prefetchable Memory Limit
Address (A[19:00]) are F_FFFFh. Thus, the bottom of the defined memory address
range are aligned to a 1 Mbyte boundary, and the top of the defined memory range are
at the top of a 1 Mbyte memory block.
The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory
Limit registers are read-only, contain the same value, and encode whether or not the
bridge supports 64-bit addresses. If these four bits have the value 0h, then the bridge
supports only 32 bit addresses. If these four bits have the value 01h, then the bridge
supports 64-bit addresses and the Prefetchable Base Upper 32 Bits and Prefetchable
Limit Upper 32 Bits registers hold the rest of the 64-bit prefetchable base and limit
addresses respectively. All other encodings are reserved.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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