EP80579 Datasheet, PDF (1179/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-15. Offset 02h: IIR - Interrupt Identification Register
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 :06
05 :04
03
02 :01
00
Bit Acronym
Bit Description
FIFOES_1_0
FIFO Mode Enable Status (bits [1:0]):
00 Non-FIFO mode is selected.
01 Reserved
10 Reserved
11 FIFO mode is selected (TRFIFOE = 1).
Reserved Reserved
TOD_IID3
Time Out Detected:
0 = No time out interrupt is pending.
1 = Time out interrupt is pending. (FIFO mode only)
IID_2_1
Interrupt Source Encoded (bits[2:1]):
00 Modem Status (CTS, DSR, RI, DCD modem
signals changed state)
01 Transmit FIFO requests data
10 Received Data Available
11 Receive error (Overrun, parity, framing, break,
FIFO error)
P_N
Interrupt Pending:
0 = Interrupt is pending. (Active low)
1 = No interrupt is pending.
Sticky
Bit Reset
Value
00b
00b
0b
00b
1b
Bit Access
RO
RO
RO
RO
Table 33-16. Interrupt Identification Register Decode (Sheet 1 of 2)
Interrupt
ID bits
Interrupt SET/RESET Function
3210
Priorit
y
Type
Source
RESET Control
0001
-
0 1 1 0 Highest
0
1
0
0
Second
Highest
1
1
0
0
Second
Highest
None
Receiver
Line Status
Received
Data
Available.
Character
Timeout
indication.
No Interrupt is pending.
Overrun Error, Parity Error,
Framing Error, Break Interrupt.
-
Reading the Line Status Register.
Non-FIFO mode: Receive Buffer Non-FIFO mode: Reading the
is full.
Receiver Buffer Register.
FIFO mode: Trigger level was
reached.
FIFO Mode only: At least 1
character is in receiver FIFO
and there was no activity for a
time period.
FIFO mode: Reading bytes until
Receiver FIFO drops below trigger
level or setting RESETRF bit in FCR
register.
Reading the Receiver FIFO or
setting RESETRF bit in FCR register.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1179