EP80579 Datasheet, PDF (230/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 2 of 4)
Offset Start Offset End
Register ID - Description
0030h
0038h
0170h
1000h
00C0h
00C4h
00C8h
00D0h
00D8h
08C0h
08C8h
08D0h
08D8h
08E0h
08E8h
08F0h
08F8h
0100h
2160h
2168h
2800h
2804h
2808h
2810h
2818h
2820h
2828h
282Ch
2C00h
5000h
5200h at 4h
5400h at 8h
5404h at 8h
5600h at 4h
0400h
0410h
0458h
3800h
3804h
0033h
003Bh
0173h
1003h
00C3h
00C7h
00CBh
00D3h
00DBh
08C3h
08CBh
08D3h
08DBh
08E3h
08EBh
08F3h
08FBh
0103h
2163h
216Bh
2803h
2807h
280Bh
2813h
281Bh
2823h
282Bh
282Fh
2C03h
5003h
5203h at 4h
5403h at 8h
5407h at 8h
5603h at 4h
0403h
0413h
045Bh
3803h
3807h
“FCT: Flow Control Type Register” on page 1451
“VET: VLAN EtherType Register” on page 1452
“FCTTV: Flow Control Transmit Timer Value Register” on page 1452
“PBA: Packet Buffer Allocation Register” on page 1453
“ICR0: Interrupt 0 Cause Read Register” on page 1454
“ITR0: Interrupt 0 Throttling Register” on page 1457
“ICS0: Interrupt 0 Cause Set Register” on page 1458
“IMS0: Interrupt 0 Mask Set/Read Register” on page 1459
“IMC0: Interrupt 0 Mask Clear Register” on page 1460
“ICR1: Interrupt 1Cause Read Register” on page 1462
“ICS1: Interrupt 0 Cause Set Register” on page 1464
“IMS1: Interrupt 1 Mask Set/Read Register” on page 1466
“IMC1: Interrupt 1 Mask Clear Register” on page 1467
“ICR2: Error Interrupt Cause Read Register” on page 1469
“ICS2: Error Interrupt Cause Set Register” on page 1471
“IMS2: Error Interrupt Mask Set/Read Register” on page 1472
“IMC2: Error Interrupt Mask Clear Register” on page 1473
“RCTL: Receive Control Register” on page 1474
“FCRTL: Flow Control Receive Threshold Low Register” on page 1478
“FCRTH: Flow Control Receive Threshold High Register” on page 1479
“RDBAL: Receive Descriptor Base Address Low Register” on page 1480
“RDBAH: Receive Descriptor Base Address High Register” on page 1480
“RDLEN: Receive Descriptor Length Register” on page 1481
“RDH: Receive Descriptor Head Register” on page 1481
“RDT: Receive Descriptor Tail Register” on page 1482
“RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483
“RXDCTL: Receive Descriptor Control Register” on page 1483
“RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485
“RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486
“RXCSUM: Receive Checksum Control Register” on page 1487
“MTA[0-127] – 128 Multicast Table Array Registers” on page 1488
“RAL[0-15] - Receive Address Low Register” on page 1488
“RAH[0-15] - Receive Address High Register” on page 1489
“VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490
“TCTL: Transmit Control Register” on page 1491
“TIPG: Transmit IPG Register” on page 1493
“AIT: Adaptive IFS Throttle Register” on page 1495
“TDBAL: Transmit Descriptor Base Address Low Register” on page 1496
“TDBAH: Transmit Descriptor Base Address High Register” on page 1496
Default
Value
00008808h
00008100h
00000000h
00100030h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
XXXXXXX0h
XXXXXXXXh
00000000h
00000000h
00000000h
00000000h
00010000h
00000000h
00000000h
00000000h
XXXX_XXXXh
XXXXXXXXh
000XXXXXh
XXXXXXXXh
00000008h
00602008h
00000000h
XXXXXXX0h
XXXXXXXXh
Intel^® EP80579 Integrated Processor Product Line Datasheet
230
August 2009
Order Number: 320066-003US