EP80579 Datasheet, PDF (1002/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.3.1
26.3.1.1
Host Controller Capability Register Details
These registers specify the limits, restrictions and capabilities of the host controller
implementation.
Within the Host Controller Capability Registers, only the Structural Parameters register
is writable. This register is implemented in the Suspend well and is only reset by the
standard suspend-well hardware reset, not by HCRESET or the D3-to-D0 reset.
Offset 00h: CAPLENGTH - Capability Length Register
This register is used as an offset to add to the Memory Base Register to find the
beginning of the Operational Register Space. This is fixed at 20h, indicating that the
Operation Registers begin at offset 20h.
Table 26-35. Offset 00h: CAPLENGTH - Capability Length Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 20h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
CRLV
Capability Register Length Value: This register is used
as an offset to add to the Memory Base Register
(D29:F7:10h) to find the beginning of the Operational
Register Space. This field is hardwired to 20h indicating
that the Operation Registers begin at offset 20h.
Bit Reset
Value
20h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1002
August 2009
Order Number: 320066-003US