EP80579 Datasheet, PDF (604/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-224.DCALCSR.OPMODS in Receive Enable Mode
Bit
Description
14:7
6:4
DRRTC override value to use in single step mode
Test point repeat number: The number of times each receive enable delay value is tested in order to
reduce the effects of noise when near a timing threshold. When set to zero, hardware will repeat each
step 8 times, the maximum number possible.
Table 16-225.DCALCSR.OPMODS in ZQ Calibration Mode
Bit
14:3
4
Ignored
=0 ZQ Calibration Long
=1 ZQ Calibration Short
Description
Table 16-226.Rules about issuing Self-Refresh and Refresh commands using
DCALCSR.OPCODE
The hardware does not enforce blocking of commands for tRFC period when a REFRESH cycle is
1 launched using the DCALCSR.OPCODE. SW is responsible for ensuring that the refresh cycle time
requirement is met.
2
Hardware will update DRC.CKE[1:0] bits with a self-refresh (SR) entry or exit command is issued
using DCALCSR.OPCODE.
3
When issuing a self-refresh entry command using DCALCSR.OPCODE, the DCALCSR.CS needs to be
set appropriately. The self-refresh entry commands will be issued on a per rank basis.
When issuing a self-refresh exit command using DCALCSR.OPCODE, the DCALCSR.CS will be ignored.
Hardware will issue the second SR exit command if a second rank is present. Also note that a a self-
4 refresh exit command using the DCALCSR.OPCODE can be issued only once per reset cycle. Hardware
does support an additional mechanism through which a self-refresh command can be issued via
DRC.CKE[1:0] (please refer to Section 11.4.5, “Self-Refresh” on page 302 for more details)
Intel^® EP80579 Integrated Processor Product Line Datasheet
604
August 2009
Order Number: 320066-003US