EP80579 Datasheet, PDF (1833/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-12. Power Sequencing Signal Timings (Sheet 2 of 2)
Sym
Parameter
Min
Max
Units Notes Fig #
t297 SLP_S5# inactive to SLP_S4# inactive
See Note 10
10
49-3
t298 SLP_S4# inactive to SLP_S3# inactive
1
2
RTCCLK
1
49-3
t299 S4 to SLP_S4# inactive
See Note 10
10
49-3
t300 S3 Wake Event to SLP_S3# inactive (S3 Wake)
0
Small as
possible
ms
1
49-3
t301 CPUSLP# inactive to STPCLK# inactive
8
PCICLK
-
49-2
Notes:
1.
These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2.
If there is no RTC battery in the system, so VCCPRTC and the VCCPSUS supplies come up together, the delay from
RTCRST# and an inactive RSMRST# prior to SUSCLK toggling may be as much as 2.5 s.
3.
STPCLK# assertion triggers the processor to send a stop grant acknowledge cycle.
4.
The EP80579 has no maximum timing requirement for this transition. It is up to the system designer to determine if the
SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
5.
If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together similar
to timing t287 (PCIRST# active to SLP_S3# active).
6.
VCC in diagram represents all core well supplies that are powered off in S3 state.
7.
VCCSus in diagram represents all sustainable supplies as identified in the Suspend power well.
8.
These transitions are clocked off the 33MHz PCICLK. 1 PCICLK is approximately 30ns.
9.
SUSCLK is an output of the RTC generator (32.768 KHz), has a duty cycle that can be as low as 30% or as high as 70%.
10.
The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the “SLP_S4#
Assertion Stretch Enable bits. Note that this does not apply for synchronous SMI’s.
11.
The relationship that the active edge of SYS_PWR_OK (platform signal connected to PWROK, PWRGD, and
SYS_PWR_OK pins) has to the active edge of VRMPWRGD/ CPU_VRD_PWR_GD in Figure 6-1 must be observed.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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